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PDF PI4IOE5V9675 Data sheet ( Hoja de datos )

Número de pieza PI4IOE5V9675
Descripción Remote 16-bit I/O expander
Fabricantes Pericom Semiconductor 
Logotipo Pericom Semiconductor Logotipo



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No Preview Available ! PI4IOE5V9675 Hoja de datos, Descripción, Manual

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Features
PI4IOE5V9675
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt
Description
Operation power supply voltage from 2.3V to 5.5V
16-bit remote I/O pins that default to inputs at power-
up
1 MHz I2C-bus interface
Compliant with the I2C-bus Fast and Standard modes
5.5V tolerant I/Os
SDA with 30 mA sink capability for 4000 pF buses
Latched outputs with 25 mA sink capability for
directly driving LEDs
Total package sink capability of 400 mA
Active LOW open-drain interrupt output
Low standby current
64 programmable slave addresses using 3 address
pins
ESD protection (4KV HBM and 1KV CDM)
Latch-up tested (exceeds 100mA)
Offered in two different packages: TSSOP-24 and
TQFN 4x4-24
The PI4IOE5V9675 provides general purpose
remote I/O expansion for most microcontroller families
via the two-line bidirectional bus (I2C-bus) and is a part
of the Fast-mode Plus family.
The PI4IOE5V9675 provides higher Fast-mode Plus
(Fm+) I2C-bus speeds (1 MHz versus 400 kHz) so that
the output can support PWM dimming of LEDs, high
I2C-bus drive (30 mA) so that many more devices can be
on the bus without the need for bus buffers, high total
package sink capacity (400 mA) that supports having all
25 mA LEDs on at the same time and more device
addresses (64) are available to allow many more devices
on the bus without address conflicts.
The device consists of a 16-bit quasi-bidirectional
port and an I2C-bus interface. The PI4IOE5V9675 has a
low current consumption and includes latched outputs
with high current drive capability for directly driving
LEDs.
It also possesses an interrupt line (INT) which can be
connected to the interrupt logic of the microcontroller.
By sending an interrupt signal on this line, the remote
I/O can inform the microcontroller if there is incoming
data on its ports without having to communicate via the
I2C-bus. The internal Power-On Reset (POR) or software
reset sequence initializes the I/Os as inputs.
Pin Configuration
Figure 1:TSSOP-24 (Top View)
2016-06-0008
Figure 2:TQFN 4x4-24(Top View)
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PI4IOE5V9675 pdf
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Dynamic Characteristics
PI4IOE5V9675
Preliminary Datasheet
16-bit I2C-bus and SMBus I/O port with interrupt
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Table 3: Dynamic characteristics
Symbol
Parameter
Standard mode I2C
Min Max
Fast mode I2C
Min Max
Fast mode
Plus I2C
Min Max
Unit
fSCL
tBUF
tHD;STA
tSU;STA
tSU;STO
tVD;ACK[1]
tHD;DAT[2]
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START condition
set-up time for a repeated START
condition
set-up time for STOP condition
data valid acknowledge time
data hold time
tVD;DAT data valid time
tSU;DAT data set-up time
tLOW LOW period of the SCL clock
tHIGH HIGH period of the SCL clock
tf fall time of both SDA and SCL signals
tr rise time of both SDA and SCL signals
tSP
pulse width of spikes that must be
suppressed by the input filter
Port timing CL≤100pF
tv(Q) Data output valid time[3]
0
4.7
4.0
4.7
4.0
-
0
-
250
4.7
4.0
-
-
-
100
-
-
-
-
3.45
-
3.45
-
-
-
300
1000
50
4
0 400 0 1000 kHz
1.3 - 0.5
μs
0.6 - 0.26
μs
0.6 - 0.26
μs
0.6 - 0.26
μs
- 0.9 - 0.45 μs
0 -0
ns
- 0.9 - 0.45 ns
100 - 50
1.3 - 0.5
0.6 - 0.26
ns
μs
μs
300 120 ns
300 120 ns
- 50
50 ns
4 4 ns
tsu(D) Data input set-up time
th(D) Data input hold time
Interrupt timing CL≤100pF
tv(INT)
Valid time on pin INT
trst(INT)
Reset time on pin INT
0
4
-4
-4
0 0 ns
4 4 μs
-4
-4
4 μs
4 μs
Note:
[1]: tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]: tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3]: tv(Q)measured from 0.7VCC on SCL to 50% I/O output.
2016-06-0008
PT0555-3
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PI4IOE5V9675 arduino
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PI4IOE5V9675
Preliminary Datasheet
16-bit I2C-bus and SMBus I/O port with interrupt
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Quasi-bidirectional I/O architecture
The PI4IOE5V9675’s 16 ports (see Figure 6) are entirely independent and can be used either as input or output ports. Input
data is transferred from the ports to the microcontroller in the Read mode. Output data is transmitted to the ports in the Write mode.
Every data transmission from the PI4IOE5V9675 must consist of an even number of bytes, the first byte will be referred to as
P07 to P00, and the second byte as P17 to P10. The third will be referred to as P07 to P00, and so on.
This quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data directions. At power-
on the I/Os are HIGH. In this mode only a current source (IOH) to VCC is active. An additional strong pull-up to VCC (Itrt(pu))
allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off
by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. After power-on, as all the I/Os are set HIGH,
all of them can be used as inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the write mode.
Remark: If a HIGH is applied to an I/O which has been written earlier to LOW, a large current (IOL) will flow to GND.
Figure 6.Simplified schematic diagram of P00 to P17
Writing to the port (Output mode)
To write, the master (microcontroller) first addresses the slave device. By setting the last bit of the byte containing the slave
address to logic 0 the Write mode is entered. The PI4IOE5V9675 acknowledges and the master sends the first data byte for P07 to
P00. After the first data byte is acknowledged by the PI4IOE5V9675, the second data byte P17 to P10 is sent by the master. Once
again, the PI4IOE5V9675 acknowledges the receipt of the data. Each 8-bit data is presented on the port lines after it has been
acknowledged by the PI4IOE5V9675.
The number of data bytes that can be sent successively is not limited. After every two bytes, the previous data is overwritten.
The first data byte in every pair refers to Port 0 (P07 to P00), whereas the second data byte in every pair refers to Port 1 (P17
to P10).
2016-06-0008
Figure 7. Correlation between bits and ports
PT0555-3
11
08/04/16

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