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PDF PI4IOE5V9539 Data sheet ( Hoja de datos )
| Número de pieza | PI4IOE5V9539 | |
| Descripción | 16-bit I2C-bus and SMBus low power I/O port | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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PI4IOE5V9539
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Features
Operation power supply voltage from 2.3V to 5.5V
16-bit I2C-bus GPIO with interrupt and reset
5V tolerant I/Os
Polarity inversion register
Active LOW interrupt output
Active LOW reset input
Low current consumption
0Hz to 400KHz clock frequency
Noise filter on SCL/SDA inputs
Power-on reset
ESD protection (4KV HBM and 1KV CDM)
Offered in two different packages: TSSOP-24 and
TQFN 4x4-24
Description
The PI4IOE5V9539 provide 16 bits of General
Purpose parallel Input/Output (GPIO) expansion for I2C-
bus/ SMBus applications. It includes the features such as
higher driving capability, 5V tolerance, lower power
supply, individual I/O configuration, and smaller
packaging. It provides a simple solution when additional
I/O is needed for ACPI power switches, sensors, push
buttons, LEDs, fans, etc.
The PI4IOE5V9539 consists of two 8-bit registers to
configure the I/Os as either inputs or outputs, and two 8-
bit polarity registers to change the polarity of the input
port register data. The data for each input or output is
kept in the corresponding Input port or Output port
register. All registers can be read by the system master.
The PI4IOE5V9539 open-drain interrupt output is
activated and indicate to the system when any input state
has changed. The power-on reset sets the registers to
their default values and initializes the device state
machine. The RESET pin causes the same reset/default
I/O input configuration to occur without de-powering the
device, holding the registers and I2C-bus state machine
in their default state until the RESET input is once again
HIGH.
Two hardware pins (A0, A1) vary the fixed I2C-bus
address and allow up to four devices to share the same
I2C-bus/SMBus.
Pin Configuration
Figure 1: TSSOP-24 ( Top View )
2016-01-0019
Figure 2: TQFN 4x4-24 ( Top View )
PT0549-3
1
02/15/16
1 page  
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Dynamic Characteristics
Table 3: Dynamic characteristics
Symbol
Parameter
fSCL
tBUF
tHD;STA
tSU;STA
tSU;STO
tVD;ACK[1]
tHD;DAT[2]
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START condition
set-up time for a repeated START
condition
set-up time for STOP condition
data valid acknowledge time
data hold time
tVD;DAT data valid time
tSU;DAT data set-up time
tLOW LOW period of the SCL clock
tHIGH HIGH period of the SCL clock
tf fall time of both SDA and SCL signals
tr rise time of both SDA and SCL signals
tSP
pulse width of spikes that must be
suppressed by the input filter
Port timing
tv(Q) Data output valid time[3]
tsu(D) Data input set-up time
th(D) Data input hold time
Interrupt timing
tv(INT)
Valid time on pin INT
trst(INT)
Reset time on pin INT
PI4IOE5V9539
16-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Test Conditions
Standard
mode I2C
Min Max
0 100
4.7 -
4.0 -
4.7 -
4.0 -
- 3.45
0-
- 3.45
250 -
4.7 -
4.0 -
- 300
- 1000
- 50
Fast mode I2C
Unit
Min Max
0 400 kHz
1.3 - μs
0.6 - μs
0.6 - μs
0.6 - μs
- 0.9 μs
0 - ns
- 0.9 ns
100 - ns
1.3 - μs
0.6 - μs
- 300 ns
- 300 ns
- 50 ns
- 200 - 200 ns
150 - 150 - ns
1 - 1 - μs
- 4 - 4 μs
- 4 - 4 μs
2016-01-0019
PT0549-3
02/15/16
5
5 Page 
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Figure 5: Simplified schematic of I/Os
PI4IOE5V9539
16-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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After power-on reset, all registers return to default values.
f. Bus Transaction
i. Writing to the port registers
Data is transmitted to the PI4IOE5V9539 by sending the device address and setting the least significant bit to a logic 0. The
command byte is sent after the address and determines which register will receive the data following the command byte. The eight
registers within the PI4IOE5V9539 are configured to operate as four register pairs. The four pairs are Input ports, Output ports,
Polarity inversion ports, and Configuration ports. After sending data to one register, the next data byte will be sent to the other
register in the pair. For example, if the first byte is sent to Output port 1 (register 3), then the next byte will be stored in Output
port 0(register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register
may be updated independently of the other registers.
Figure 6: Write to output registers
2016-01-0019
PT0549-3
02/15/16
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet PI4IOE5V9539.PDF ] | |
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