|
|
PDF PI4IOE5V9535 Data sheet ( Hoja de datos )
| Número de pieza | PI4IOE5V9535 | |
| Descripción | 16-bit I2C-bus and SMBus I/O port | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PI4IOE5V9535 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
PI4IOE5V9535
16-bit I2C-bus and SMBus I/O port with interrupt
Features
Operation power supply voltage from 2.3V to 5.5V
16-bit I/O pins which can be programmed as Input
or Output
5V tolerant I/Os
Polarity inversion register
Active LOW interrupt output
Low current consumption
0Hz to 400KHz clock frequency
Noise filter on SCL/SDA inputs
Power-on reset
ESD protection (4KV HBM and 1KV CDM)
Latch-up tested (exceeds 100mA)
Offered in two different packages: TSSOP-24 and
TQFN 4x4-24
Description
The PI4IOE5V9535 is a 24-pin device that
provides 16 bits of General Purpose parallel
Input/Output (GPIO) expansion for I2C-bus/SMBus
applications It includes the features such as higher
driving capability, 5V tolerance, lower power supply,
individual I/O configuration, and smaller packaging. It
provides a simple solution when additional I/O is
needed for ACPI power switches, sensors, push
buttons, LEDs, fans, etc.
The PI4IOE5V9535 consists of two 8-bit
Configuration (Input or Output selection), Input,
Output and Polarity Inversion (active HIGH or active
LOW operation) registers. The system master can
enable the I/Os as either inputs or outputs by writing to
the I/O configuration bits. The data for each input or
output is kept in the corresponding Input port or
Output port register. The polarity of the read register
can be inverted with the Polarity Inversion register. All
registers can be read by the system master.
The PI4IOE5V9535 is identical to the
PI4IOE5V9555 except for the removal of the internal
I/O pull-up resistor which greatly reduces power
consumption when the I/Os are held LOW.
The PI4IOE5V9535 open-drain interrupt output is
activated when any input state differs from its
corresponding Input Port register state and is used to
indicate to the system master that an input state has
changed. The power-on reset sets the registers to their
default values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed
I2C-bus address and allow up to eight devices to share
the same I2C-bus/SMBus. The fixed I2C-bus address
of the PI4IOE5V9535 are the same as the
PI4IOE5V9535 allowing up to eight of these devices
in any combination to share the same I2C-bus/SMBus.
Pin Configuration
Figure 1: TSSOP-24 ( Top View )
2016-01-0026
Figure 2: TQFN 4x4-24 ( Top View )
PT0561-2
1
02/15/16
1 page  
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||
Dynamic Characteristics
PI4IOE5V9535
16-bit I2C-bus and SMBus I/O port with interrupt
|||||||||||||||||
Table 3: Dynamic characteristics
Symbol
Parameter
Test Conditions
Standard
mode I2C
Min Max
Fast mode I2C
Unit
Min Max
fSCL
tBUF
tHD;STA
tSU;STA
tSU;STO
tVD;ACK[1]
tHD;DAT[2]
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START condition
set-up time for a repeated START
condition
set-up time for STOP condition
data valid acknowledge time
data hold time
tVD;DAT data valid time
tSU;DAT data set-up time
tLOW LOW period of the SCL clock
tHIGH HIGH period of the SCL clock
tf fall time of both SDA and SCL signals
tr rise time of both SDA and SCL signals
tSP
pulse width of spikes that must be
suppressed by the input filter
Port timing
tv(Q) Data output valid time[3]
tsu(D) Data input set-up time
th(D) Data input hold time
0 100 0 400 kHz
4.7 - 1.3 - μs
4.0 - 0.6 - μs
4.7 - 0.6 - μs
4.0 -
- 3.45
0.6
-
- μs
0.9 μs
0 - 0 - ns
- 3.45
-
0.9 ns
250 -
4.7 -
4.0 -
100 - ns
1.3 - μs
0.6 - μs
- 300
- 300 ns
- 1000 - 300 ns
- 50
- 50 ns
- 200 - 200 ns
150 - 150 - ns
1 - 1 - μs
Interrupt timing
tv(INT)
Valid time on pin INT
trst(INT)
Reset time on pin INT
- 4 - 4 μs
- 4 - 4 μs
Note:
[1]: tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.
[2]: tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3]: tv(Q)measured from 0.7VCC on SCL to 50% I/O output.
2016-01-0026
PT0561-2
02/15/16
5
5 Page 
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||
Write to Output port register
Figure 7: Write to configuration registers
PI4IOE5V9535
16-bit I2C-bus and SMBus I/O port with interrupt
|||||||||||||||||
ii. Reading the port registers
In order to read data from the PI4IOE5V9535, the bus master must first send the PI4IOE5V9535 address with the least
significant bit set to a logic 0. The command byte is sent after the address and determines which register will be accessed. After a
restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from the register defined by
the command byte will then be sent by the PI4IOE5V9535. Data is clocked into the register on the falling edge of the acknowledge
clock pulse. After the first byte is read, additional bytes may be read but the data will now reflect the information in the other
register in the pair. For example, if you read Input Port 1, then the next byte read would be Input Port 0. There is no limitation on
the number of data bytes received in one read transmission but the final byte received, the bus master must not acknowledge the
data.
Figure 8: Read from registers
Note: Transfer can be stopped at any time by a STOP condition.
2016-01-0026
PT0561-2
02/15/16
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet PI4IOE5V9535.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PI4IOE5V9535 | 16-bit I2C-bus and SMBus I/O port | Pericom Semiconductor |
| PI4IOE5V9536 | 4-bit I2C-bus and SMBus low power I/O port | Pericom Semiconductor |
| PI4IOE5V9537 | 4-bit I2C-bus and SMBus low power I/O port | Pericom Semiconductor |
| PI4IOE5V9539 | 16-bit I2C-bus and SMBus low power I/O port | Pericom Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |