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PDF PI4IOE5V9521 Data sheet ( Hoja de datos )
| Número de pieza | PI4IOE5V9521 | |
| Descripción | 2-bit I2C-bus and SMBus low power I/O port | |
| Fabricantes | Pericom Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PI4IOE5V9521 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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PI4IOE5V9521
2-bit I2C-bus and SMBus low power I/O port with interrupt and reset
Features
Operation power supply voltage from 2.3V to 5.5V
2-bit I2C-bus GPIO with interrupt and reset
5V tolerant I/Os
Active Low interrupt output
Active Low reset input
Polarity inversion register
Low current consumption
0Hz to 1MHz clock frequency
Noise filter on SCL/SDA inputs
Power-on reset
ESD protection (4KV HBM and 1KV CDM)
Package offered :UQFN 1.6x1.6-8
Pin Configuration
Description
The PI4IOE5V9521 provides 2 bits of General
Purpose parallel Input/Output (GPIO) expansion for
I2C-bus/ SMBus applications. It includes the features
such as higher driving capability, 5V tolerance, lower
power supply, individual I/O configuration, and
smaller packaging. It provides a simple solution when
additional I/O is needed for ACPI power switches,
sensors, push buttons, LEDs, fans, etc.
The PI4IOE5V9521 consists of a 2-bit
configuration register to configure the I/Os as either
inputs or outputs, and a 2-bit polarity register to change
the polarity of the input port register data. The data for
each input or output is kept in the corresponding Input
port or Output port register. All registers can be read
by the system master.
The PI4IOE5V9521 open-drain interrupt output
(INT) is activated when any input state is differed from
its corresponding Input Port register and is used to
indicate the system master that an input state has
changed.
The power-on reset sets the registers to their
default values and initializes the device state machine.
The Reset pin (Reset) causes the same
reset/initialization to occur without de-powering the
device.
Figure 1. UQFN 1.6 x 1.6-8
2016-02-0002
1
PT0564-1
03/29/16
1 page  
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Dynamic characteristics
PI4IOE5V9521
2-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Table 3: Dynamic characteristics
Symbol
Parameter
Conditions
Standard mode
I2C
Min Max
Fast mode
I2C
Min Max
Fast mode Plus
I2C
Min Max
Unit
fSCL
tBUF
tHD;STA
tSU;STA
tSU;STO
tVD;ACK[1]
tHD;DAT[2]
tVD;DAT
SCL clock frequency
Bus free time between a STOP
and START condition
Hold time (repeated) START
condition
Set-up time for a repeated
START condition
Set-up time for STOP condition
Data valid acknowledge time
Data hold time
Data valid time
tSU;DAT Data set-up time
tLOW LOW period of the SCL clock
tHIGH HIGH period of the SCL clock
tf
Fall time of both SDA and SCL
signals
tr
Rise time of both SDA and SCL
signals
tSP
Pulse width of spikes that must
be suppressed by the input filter
Port timing
tv(Q) Data output valid time[3]
tsu(D) Data input set-up time
th(D) Data input hold time
Interrupt timing
tv(INT) Valid time on pin INT
trst(INT) Reset time on pin INT
0 100 0 400 0 1000 kHz
4.7 - 1.3 - 0.5 - μs
4.0 - 0.6 - 0.26 - μs
4.7 - 0.6 - 0.26 - μs
4.0 - 0.6
- 3.45 -
- 0.26 - μs
0.9 - 0.45 μs
0 - 0 - 0 - ns
- 3.45 - 0.9 - 0.45 us
250 - 100 - 50 - ns
4.7 - 1.3 - 0.5 - μs
4.0 - 0.6 - 0.26 - μs
- 300 - 300 - 120 ns
- 1000 - 300 - 120 ns
- 50 - 50
50 ns
- 200 - 200 - 200 ns
100 - 100 - 100 - ns
1 - 1 - 1 - μs
- 4 - 4 - 4 μs
- 4 - 4 - 4 μs
2016-02-0002
PT0564-1
03/29/16
5
5 Page 
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Figure 8: Read Input port register
PI4IOE5V9521
2-bit I2C-bus and SMBus
low power I/O port with interrupt and reset
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Note: Transfer of data can be stopped at any moment by a STOP condition. It is assumed that the command byte has
previously been set to ‘00’ (read Input Port register).
Application design-in information
Figure 9: Typical application
2016-02-0002
PT0564-1
03/29/16
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet PI4IOE5V9521.PDF ] | |
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