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PDF AK4372 Data sheet ( Hoja de datos )
| Número de pieza | AK4372 | |
| Descripción | DAC | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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[AK4372]
AK4372
DAC with built-in PLL & HP-AMP
GENERAL DESCRIPTION
The AK4372 is a 24-bit DAC with an integrated PLL and headphone amplifier. The PLL input frequency is
synchronized to typical mobile phone clock frequencies. The AK4372 features an analog mixing circuit
that allows easy interfacing in mobile phone and portable communication designs. The integrated
headphone amplifier features “pop-noise free” power-on/off, a mute control, and it delivers 40mW of
power into 16Ω. The AK4372 is packaged in a 24-pin CSP (2.5mm×2.5mm) package, ideal for portable
applications.
FEATURE
Multi-bit ΔΣ DAC
Sampling Rate
- 8kHz ~ 48kHz
On chip perfect filtering 8 times FIR interpolator
- Passband: 20kHz
- Passband Ripple: ±0.02dB
- Stopband Attenuation: 54dB
Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz
System Clock
- PLL Mode (MCKI): 27MHz, 26MHz, 19.8MHz, 19.68MHz, 19.2MHz, 15.36MHz,
14.4MHz, 13MHz, 12MHz and 11.2896MHz
- PLL Mode (BICK or LRCK): 64fs, 32fs or fs
- EXT Mode: 256fs/384fs/512fs/768fs/1024fs
- Input Level: AC Couple Input Available
Audio I/F Format: MSB First, 2’s Complement
- I2S, 24bit MSB justified, 24bit/20bit/16bit LSB justified
- Master/Slave Mode
Digital Mixing: LR, LL, RR, (L+R)/2
Bass Boost Function
Digital ATT
Analog Mixing Circuit: 3 Inputs (Single-ended or Full-differential)
Stereo Lineout
- S/N: [email protected]
- Output Volume: +6 to –24dB (or 0 to –30dB), 2dB step
Headphone Amplifier
- Output Power: 40mW x 2ch @16Ω, 3.3V
- S/N: [email protected]
- Pop Noise Free at Power-ON/OFF and Mute
- Output Volume: 0 ~ –63dB & +12/+6/0 dB Gain
1.5dB step (0 ~ –30dB), 3dB step (–30 ~ –63dB)
μP Interface: 3-wire/I2C
Power Supply: 1.6V ∼ 3.6V
Power Supply Current: 3.8mA @1.8V (6.8mW, DAC+HP, No output)
AK4372ECB: Ta= −30 ∼ 85°C
AK4372VCB: Ta= −40 ∼ 85°C
Small Package: 24pin CSP (2.5mm x 2.5mm, 0.4mm pitch)
Register Compatible with AK4368
MS0684-E-02
-1-
2008/12
1 page  
[AK4372]
PIN/FUNCTION
No. Pin Name I/O
Function
A1 SDATA
I Audio Serial Data Input Pin
B2 BICK
I/O Audio Serial Data Clock Pin
B3 LRCK
I/O Input / Output Channel Clock Pin
A3 MCKI
I External Master Clock Input Pin
C3 DVDD
- Digital Power Supply Pin, 1.6 ∼ 3.6V
A4 VCOC
O
Output for Loop Filter of PLL Circuit
This pin must be connected to VSS2 with one resistor and one capacitor in series.
A5 VSS2
- Ground 2 Pin. Connected to VSS1.
B4 MCKO
O Master Clock Output Pin
C4
SDA
CDTI
I/O Control Data Input/Output Pin (I2C mode : I2C pin = “H”)
I Control Data Input Pin (3-wire serial mode : I2C pin = “L”)
B5
SCL
CCLK
I Control Data Clock Pin (I2C mode : I2C pin = “H”)
I Control Data Clock Pin (3-wire serial mode : I2C pin = “L”)
C5
CAD0
CSN
I Chip Address 0 Select Pin (I2C mode : I2C pin = “H”)
I Chip Select Pin (3-wire serial mode : I2C pin = “L”)
Power-down & Reset
D5 PDN
I When “L”, the AK4372 is in power-down mode and is held in reset.
The AK4372 must be reset once upon power-up.
D3 I2C
I
Control Mode Select Pin
“H”: I2C Bus, “L”: 3-wire Serial
E5 MUTET
O
Mute Time Constant Control pin
Connected to the VSS1 pin with a capacitor for mute time constant.
D4 LOUT
O Lch Stereo Line Output Pin
E4 ROUT
O Rch Stereo Line Output Pin
E3 VCOM
O
Common Voltage Output Pin
Normally connected to the VSS1 pin with a 2.2μF electrolytic capacitor.
E2 AVDD
- Analog & PLL Power Supply Pin, 1.6 ∼ 3.6V
E1 VSS1
- Ground 1 Pin
D2 HPR
O Rch Headphone Amp Output
D1 HPL
O Lch Headphone Amp Output
C1 MIN
I Mono Analog Input Pin
B1
RIN
IN+
I Rch Analog Input Pin (LDIF bit =“0” : Single-ended Input)
I Positive Line Input Pin (LDIF bit =“1” : Full-differential Input)
C2
LIN
IN−
I Rch Analog Input Pin (LDIF bit =“0” : Single-ended Input)
I Negative Line Input Pin (LDIF bit =“1” : Full-differential Input )
Note 1. All digital input pins (I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) must not
be left floating. The MCKI pin can be left floating only when the PDN pin = “L”.
MS0684-E-02
-5-
2008/12
5 Page 
[AK4372]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD = DVDD=1.6 ∼ 3.6V; CL = 20pF; unless otherwise specified)
Parameter
Symbol
min
Master Clock Input Timing
Frequency (PLL mode)
(EXT mode)
Pulse Width Low (Note 22)
Pulse Width High (Note 22)
AC Pulse Width (Note 23)
fCLK
fCLK
tCLKL
tCLKH
tACW
11.2896
2.048
0.4/fCLK
0.4/fCLK
18.5
LRCK Timing
Frequency
Duty Cycle: Slave Mode
fs
Duty
8
45
Master Mode
Duty
-
MCKO Output Timing (PLL mode)
Frequency
Duty Cycle (Except fs=32kHz, PS1-0= “00”)
fCLKO
dMCK
0.256
40
(fs=32kHz, PS1-0= “00”)
dMCK
-
Serial Interface Timing (Note 24)
Slave Mode (M/S bit = “0”):
BICK Period (Note 25)
(Except PLL Mode,
PLL4-0 bit = “01110”, “01111”)
(PLL Mode, PLL4-0 bits = “01110”)
(PLL Mode, PLL4-0 bits = “01111”)
BICK Pulse Width Low
(Except PLL Mode,
PLL4-0 bit = “01110”, “01111”)
(PLL Mode,
PLL4-0 bit = “01110”, “01111”)
BICK Pulse Width High
(Except PLL Mode,
PLL4-0 bit = “01110”, “01111”)
(PLL Mode,
PLL4-0 bit = “01110”, “01111”)
LRCK Edge to BICK “↑” (Note 26)
BICK “↑” to LRCK Edge (Note 26)
SDATA Hold Time
tBCK
tBCK
tBCK
312.5 or 1/(64fs)
-
-
tBCKL
tBCKL
100
0.4 x tBCK
tBCKH
tBCKH
tLRB
tBLR
tSDH
100
0.4 x tBCK
50
50
50
SDATA Setup Time
tSDS
50
Master Mode (M/S bit = “1”):
BICK Frequency (BF bit = “1”)
(BF bit = “0”)
fBCK
fBCK
-
-
BICK Duty
BICK “↓” to LRCK
SDATA Hold Time
SDATA Setup Time
dBCK
tMBLR
tSDH
tSDS
-
−50
50
50
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
CDTI Hold Time
tCDS
tCDH
40
40
CSN “H” Time
tCSW
150
CSN Edge to CCLK “↑” (Note 27)
CCLK “↑” to CSN Edge (Note 27)
tCSS
tCSH
50
50
typ max
- 27
- 24.576
--
--
--
44.1 48
- 55
50 -
- 12.288
- 60
33 -
- 1/(32fs)
1/(32fs)
-
1/(64fs)
-
--
--
--
--
--
--
--
--
64fs -
32fs -
50 -
- 50
--
--
--
--
--
--
--
--
--
--
Units
MHz
MHz
ns
ns
ns
kHz
%
%
MHz
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
Hz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MS0684-E-02
- 11 -
2008/12
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AK4372.PDF ] | |
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