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Número de pieza | AK4370 | |
Descripción | 24-Bit 2ch DAC | |
Fabricantes | AKM | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de AK4370 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! [AK4370]
AK4370
24-Bit 2ch DAC with HP-AMP & Output Mixer
GENERAL DESCRIPTION
The AK4370 is a 24-bit DAC with headphone amplifier. The AK4370 features an analog mixing circuit
that allows easy interfacing in mobile phone and portable communication designs. The integrated
headphone amplifier features “pop-noise free” power-on/off, a mute control, and it delivers 40mW of
power into 16. The AK4370 is packaged in a 24-pin QFN (4mm×4mm) package, ideal for portable
applications.
FEATURE
Multi-bit DAC
Sampling Rate
- 8kHz 48kHz
On chip perfect filtering 8 times FIR interpolator
- Passband: 20kHz
- Passband Ripple: 0.02dB
- Stopband Attenuation: 54dB
Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz
System Clock
- 256fs/384fs/512fs/768fs/1024fs
- Input Level: AC Couple Input Available
Audio I/F Format: MSB First, 2’s Complement
- I2S, 24bit MSB justified, 24bit/20bit/16bit LSB justified
- Master/Slave Mode
Digital Mixing: LR, LL, RR, (L+R)/2
Bass Boost Function
Digital ATT
Analog Mixing Circuit: 4 Inputs (Single-ended or Full-differential)
Stereo Lineout
- S/N: [email protected]
- Output Volume: +6 to –24dB (or 0 to –30dB), 2dB step
Headphone Amplifier
- Output Power: 40mW x 2ch @16, 3.3V
- S/N: [email protected]
- Pop Noise Free at Power-ON/OFF and Mute
- Output Volume: 0 ~ –63dB & +12/+6/0 dB Gain
1.5dB step (0 ~ –30dB), 3dB step (–30 ~ –63dB)
P Interface: 3-wire/I2C
Power Supply: 1.6V 3.6V
Power Supply Current: 3.8mA @1.8V (6.8mW, DAC+HP, No output)
Ta: 30 85C
Small Package: 24-pin QFN (4mm x 4mm, 0.5mm pitch)
Register Compatible with AK4368
MS0595-E-02
-1-
2015/11
1 page [AK4370]
PIN/FUNCTION
No. Pin Name I/O
Function
1 SDATA
I Audio Serial Data Input Pin
2 BICK
I/O Audio Serial Data Clock Pin
3 LRCK
I/O Input / Output Channel Clock Pin
4 MCKI
I External Master Clock Input Pin
5 DVDD
- Digital Power Supply Pin, 1.6 3.6V
6 VSS2
7
SDA
CDTI
8
SCL
CCLK
9
CAD0
CSN
- Ground 2 Pin. Connected to VSS1.
I/O Control Data Input/Output Pin (I2C mode : I2C pin = “H”)
I Control Data Input Pin (3-wire serial mode : I2C pin = “L”)
I Control Data Clock Pin (I2C mode : I2C pin = “H”)
I Control Data Clock Pin (3-wire serial mode : I2C pin = “L”)
I Chip Address 0 Select Pin (I2C mode : I2C pin = “H”)
I Chip Select Pin (3-wire serial mode : I2C pin = “L”)
10 PDN
Power-down & Reset
I When “L”, the AK4370 is in power-down mode and is held in reset.
The AK4370 should always be reset upon power-up.
11 I2C
I
Control Mode Select Pin
“H”: I2C Bus, “L”: 3-wire Serial
12 MUTET
O
Mute Time Constant Control pin
Connected to VSS1 pin with a capacitor for mute time constant.
13 LOUT
O Lch Stereo Line Output Pin
14 ROUT
O Rch Stereo Line Output Pin
15 VCOM
O
Common Voltage Output Pin
Normally connected to VSS1 pin with a 2.2F electrolytic capacitor.
16 AVDD
- Analog Power Supply Pin, 1.6 3.6V
17 HVDD
- Power Supply Pin for Headphone Amp, 1.6 3.6V
18 VSS1
- Ground 1 Pin
19 HPR
O Rch Headphone Amp Output
20 HPL
O Lch Headphone Amp Output
21 RIN2
I Rch Analog Input 2 Pin
22 LIN2
23
RIN1
IN+
24
LIN1
IN−
I Lch Analog Input 2 Pin
I Rch Analog Input 1 Pin (LDIF bit =“0” : Single-ended Input)
I Positive Line Input Pin (LDIF bit =“1” : Full-differential Input)
I Rch Analog Input 1 Pin (LDIF bit =“0” : Single-ended Input)
I Negative Line Input Pin (LDIF bit =“1” : Full-differential Input)
Note 1. All digital input pins (I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) must not
be left floating. MCKI pin can be left floating only when PDN pin = “L”.
MS0595-E-02
-5-
2015/11
5 Page [AK4370]
SWITCHING CHARACTERISTICS
(Ta=25C; AVDD, DVDD, HVDD=1.6 3.6V; CL = 20pF; unless otherwise specified)
Parameter
Symbol
Min.
Typ. Max. Unit
Master Clock Input Timing
Frequency
fCLK
2.048
- 24.576 MHz
Pulse Width Low (Note 22)
tCLKL
0.4/fCLK
- - ns
Pulse Width High (Note 22)
tCLKH
0.4/fCLK
- - ns
AC Pulse Width (Note 23)
tACW
20.3
- - ns
LRCK Timing
Frequency
fs 8 44.1 48 kHz
Duty Cycle: Slave Mode
Duty 45 - 55
Master Mode
Duty
- 50 - %
Serial Interface Timing (Note 24)
Slave Mode (M/S bit = “0”):
BICK Period (Note 25)
tBCK
312.5 or 1/(64fs)
- 1/(32fs) ns
BICK Pulse Width Low
tBCKL
100
- - ns
Pulse Width High
LRCK Edge to BICK “” (Note 26)
BICK “” to LRCK Edge (Note 26)
tBCKH
tLRB
tBLR
100
50
50
- - ns
- - ns
- - ns
SDATA Hold Time
tSDH 50 - - ns
SDATA Setup Time
tSDS 50 - - ns
Master Mode (M/S bit = “1”):
BICK Frequency (BF bit = “1”)
(BF bit = “0”)
fBCK
fBCK
-
64fs -
Hz
-
32fs -
Hz
BICK Duty
BICK “” to LRCK
dBCK
- 50 - %
tMBLR
50
- 50 ns
SDATA Hold Time
tSDH 50 - - ns
SDATA Setup Time
tSDS 50 - - ns
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK 200 - - ns
CCLK Pulse Width Low
tCCKL
80
- - ns
Pulse Width High
tCCKH
80
- - ns
CDTI Setup Time
tCDS 40 - - ns
CDTI Hold Time
CSN “H” Time
CSN “” to CCLK “”
CCLK “” to CSN “”
tCDH 40 - - ns
tCSW 150 - - ns
tCSS 50 - - ns
tCSH 50 - - ns
Note 22. Except AC coupling.
Note 23. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to ground.
(Refer to Figure 3.)
Note 24. Refer to “Serial Data Interface”.
Note 25. Min is longer value between 312.5ns or 1/(64fs) except for PLL Mode, PLL4-0 bits = “EH”, “FH”.
Note 26. BICK rising edge must not occur at the same time as LRCK edge.
MS0595-E-02
- 11 -
2015/11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet AK4370.PDF ] |
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