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PDF STL7N10F7 Data sheet ( Hoja de datos )
| Número de pieza | STL7N10F7 | |
| Descripción | N-channel Power MOSFET | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STL7N10F7
N-channel 100 V, 0.027 Ω typ., 7 A STripFET™ VII DeepGATE™
Power MOSFET in a PowerFLAT™ 3.3x3.3 package
Datasheet - production data
Features
1
2
3
4
PowerFLAT™ 3.3x3.3
Figure 1. Internal schematic diagram
D(5, 6, 7, 8)
8 76 5
G(4)
Order code
STL7N10F7
VDS
100 V
RDS(on) max
0.035 Ω
ID
7A
• N-channel enhancement mode
• Lower RDS(on) x area vs previous generation
• 100% avalanche rated
Applications
• Switching applications
Description
th
This device utilizes the 7 generation of design
rules of ST’s proprietary STripFET™ technology,
with a new gate structure. The resulting Power
MOSFET exhibits the lowest RDS(on) in all
packages.
S(1, 2, 3)
1234
AM15810v1
Order code
STL7N10F7
Table 1. Device summary
Marking
Package
7N10F
PowerFLAT™ 3.3x3.3
Packaging
Tape and reel
April 2014
This is information on a product in full production.
DocID025972 Rev 2
1/14
www.st.com
1 page  
STL7N10F7
Electrical characteristics
Symbol
Table 7. Source drain diode
Parameter
Test conditions
Min. Typ. Max. Unit
ISD
(1)
ISDM
(2)
VSD
trr
Qrr
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
IRRM Reverse recovery current
ISD= 7 A, VGS=0
ISD= 7 A,
di/dt = 100 A/μs,
VDD= 80 V, Tj=150 °C
(see Figure 18)
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 μs, duty cycle 1.5 %
- 7A
- 28 A
- 1.1 V
- 38
ns
- 29
nC
- 1.7
A
DocID025972 Rev 2
5/14
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5 Page 
STL7N10F7
Dim.
A
b
c
D
D1
D2
e
E
E1
E2
H
K
L
L1
L2
ϑ
Package mechanical data
Table 8. PowerFLAT™ 3.3 x 3.3 mechanical data
mm
Min.
Typ.
0.70 0.80
0.25 0.30
0.14 0.15
3.10 3.30
3.05 3.15
2.15 2.25
0.55 0.65
3.10 3.30
2.90 3.00
1.60 1.70
0.25 0.40
0.65 0.75
0.30 0.45
0.05 0.15
8° 10°
Max.
0.90
0.39
0.20
3.50
3.25
2.35
0.75
3.50
3.10
1.80
0.55
0.85
0.60
0.25
0.15
12°
DocID025972 Rev 2
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