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PDF TS80000 Data sheet ( Hoja de datos )
| Número de pieza | TS80000 | |
| Descripción | High Efficiency Transmitter Controller | |
| Fabricantes | Semtech | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TS80000 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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TS80000
High Efficiency Transmitter Controller
for Wireless Power Systems
TRIUNE PRODUCTS
Features
• Supports Qi®, PMA and proprietary charging applications
• Power outputs up to 40W+
• Support for single and multi-coil applications
• Support for half and full-bridge power sections
• Support for variable voltage, variable frequency and
variable duty cycle architectures
• Integrated controller and flash for communications and
control
• High precision data converters
• Precise control of bridge duty cycle and frequency
• Low external component count
Applications
• RISC-based controller core with flash and SRAM memory
• Two 12-bit A/D converters
• DMA controller
• Three 16-bit timers, each with up to 4 IC/OC/PWM or pulse
counter
• Dual 16-bit PWM timers with dead-time generation
• 3 AGPIO and 5 GPIO for application customization
• I2C or UART interface
• USB interface
• 36 pin 6x6 QFN
Description
The TS80000 is a power transmitter communications and
control unit for wireless charging applications. The TS80000
can support power outputs up to 40W+, and supports Qi®
compliant, PMA compliant and proprietary applications.
The TS80000 can be configured to drive single or multi-coil
applications, in half and full-bridge systems.
The TS80000 performs the necessary decode of packets from
the secondary side device and adjusts the control accordingly.
An integrated PID filter provides the necessary compensation
for the loop for high-precision control of duty cycle, frequency,
and or bridge voltage.
Applications
• Qi® , PMA and non-standard wireless chargers for:
Cell Phones and Smartphones
GPS Devices
Digital Cameras
Tablets and eReaders
Portable Lighting
Industrial applications
• Automotive chargers
OEM in-cabin chargers
Charging accessories
Typical Application Circuit
DC
Supply
Application
Processor
TS80000
+
TS61001
TS81000
+
TS51111
Application
Processor
Load
Transmitter
Receiver
TS80000
Final Datasheet
March 19, 2015
Rev 1.4
www.semtech.com
1 of 37
Semtech
Proprietary & Confidential
1 page  
Absolute Maximum Rating
Over operating free–air temperature range unless otherwise noted (1,2,3)
Parameter
VDD, AVDD, GND, AGND (supply voltage)
OSC_IN, OSC_OUT, DRV_EN, PWM1_H, PWM2_H, GPIO10, GPIO11/USBD_N, GPIO12/
USBD_P, GPIO13/JTMS, GPIO3, GPIO4, SCL/TXD, SDA/RXD
NRST, THERM/FOD, AGPIO1, AGPIO2/AC1_VOLTAGE, AGPIO3/AC2_VOLTAGE, AC3_
VOLTAGE, DC_VOLTAGE, DC_CURRENT, PWM1_L, PWM2_L, AC_MAX, GPIO14/JTCK,
GPIO15, GPIO5
Operating Junction Temperature Range, TJ
Min Max
-0.3 4.0
GND - 0.3 VDD + 4.0
Unit
V
V
GND - 0.3
-40
4.0
125
V
°C
Storage Temperature Range, TSTG
-65 150
°C
Electrostatic Discharge – Human Body Model
±2k V
Lead Temperature (soldering, 10 seconds)
260 °C
Notes:
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating condi-
tions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.
Operating Conditions
Parameter
Input Operating Voltage
Oscillator Frequency
Analog Supply decoupling capacitor values
Digital Supply decoupling capacitor values
Operating Free Air Temperature
Operating Junction Temperature
Symbol
VDD / AVDD
FOSC
AVDD
VDD
TA
TJ
Min.
2.0
-40
-40
Typ.
3.3
8.0
100
4.7
4.7
3 x 100
4.7
Max.
3.6
85
105
Units
V
MHz
nF
nF
uF
nF
uF
°C
°C
Communication Interfaces
The Applications Processor can interrogate the TS8000x using the I2C or UART interface. The two interfaces share the same pins.
Only one interface is active at any time.
TS80000
Final Datasheet
March 19, 2015
Rev 1.4
www.semtech.com
5 of 37
Semtech
Proprietary & Confidential
5 Page 
Status0 Register (STATUS0)
Address:
Reset value:
0x08
0xC0
Bit 7 CTS: Clear To Send
This bit indicates if a new read/write register access can be issued to the controller. This bit
is not reset by hardware when read.
0: The controller is busy processing a previous register access. New commands should not
be sent to the controller.
1: The controller can accept a new register access command over the communication
interface.
Bit 6 CTS_API: Clear to Send for API
This bit indicates if a new API call or API read request can be issued to the controller. This
bit is not reset by hardware when read.
0: The controller is busy processing a previous API call. New API calls should not be sent to
the controller.
1: The controller can accept a new API call over the communication interface.
Bit 5 CTS_IF: Clear To Send Event Interrupt Flag
0: No event is signaled for the CTS bit or the corresponding bit in the INTERRUPT_MASK0
register is cleared.
1: The CTS bit has been set and the corresponding bit in the INTERRUPT_MASK0 register is
set. Reset to 0 by hardware when the STATUS0 register is read.
Bit 4 CTS_API_IF: Clear to Send for API Event Interrupt Flag
0: No event is signaled for the CTS_API bit.
1: The CTS_API bit has been set and the corresponding bit in the INTERRUPT_MASK0
register is set. Reset to 0 by hardware when the STATUS0 register is read.
Bit 3 STATUS3_IF: STATUS1 Event Interrupt Flag
0: No event is signaled in the STATUS3 register or the corresponding bit in the INTERRUPT_
MASK0 register is cleared.
1: An event is signaled in the STATUS3 register and the corresponding bit in the
INTERRUPT_MASK3 register is set. Reset to 0 by hardware when the STATUS3 register is read.
Bit 2 STATUS2_IF: STATUS2 Event Interrupt Flag
0: No event is signaled in the STATUS2 register or the corresponding bit in the INTERRUPT_
MASK0 register is cleared.
1: An event is signaled in the STATUS2 register and the corresponding bit in the
INTERRUPT_MASK2 register is set. Reset to 0 by hardware when the STATUS2 register is read.
Bit 1 STATUS1_IF: STATUS1 Event Interrupt Flag
0: No event is signaled in the STATUS1 register or the corresponding bit in the INTERRUPT_
MASK0 register is cleared.
1: An event is signaled in the STATUS1 register and the corresponding bit in the
INTERRUPT_MASK1 register is set. Reset to 0 by hardware when the STATUS1 register is read.
Bit 0 Reserved
TS80000
Final Datasheet
March 19, 2015
Rev 1.4
www.semtech.com
11 of 37
Semtech
Proprietary & Confidential
11 Page | ||
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