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PDF COP988GD Data sheet ( Hoja de datos )
| Número de pieza | COP988GD | |
| Descripción | 8-Bit CMOS ROM Based Microcontrollers with 16k | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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July 1999
COP888GD
8-Bit CMOS ROM Based Microcontrollers with 16k
Memory and 8-Channel A/D
General Description
The COP888GD ROM based microcontrollers are highly in-
tegrated COP8™ Feature core devices with 16k memory
and advanced features including an A/D Converter. These
multi-chip CMOS devices are suited for applications requir-
ing a full featured controller with an 8-bit A/D converter, and
as pre-production devices for a masked ROM design. Pin
and software compatible 16k or 32k OTP EPROM versions
are available (COP87L88GD/RD Family) for pre-production,
and for use with a range of COP8 software and hardware de-
velopment tools.
Family features include an 8-bit memory mapped architec-
ture, 10 MHz CKI with 1µs instruction cycle, three multi-
function 16-bit timer/counters, MICROWIRE/PLUS™ serial
I/O, one 8-bit/8-channel A/D converter with prescaler and
both differential and single ended modes, two power saving
HALT/IDLE modes, MIWU, idle timer, high current outputs,
software selectable I/O options, WATCHDOG™ timer and
Clock Monitor, 2.5V to 5.5V operation, program code secu-
rity, and 44 pin package.
Devices included in this datasheet are:
Device
COP688GD
COP888GD
COP988GD
Memory (bytes)
16k ROM
16k ROM
16k ROM
RAM (bytes)
256
256
256
I/O Pins
40
40
40
Packages
44 PLCC
44 PLCC
44 PLCC
Temperature
-55 to +125˚C
-40 to +85˚C
0 to +70˚C
Comments
4.5V to 5.5V
2.5V to 5.5V
2.5V to 4.0V, GDH = 4.0V to
6.0V
Key Features
n 8-channel A/D converter with prescaler and both
differential and single ended modes
n Three 16-bit timers, each with two 16-bit registers
supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n Quiet design (low radiated emissions)
n 16 kbytes on-board ROM
n 256 bytes on-board RAM
Additional Peripheral Features
n Idle Timer
n Multi-Input Wakeup (MIWU) with optional interrupts (8)
n WATCHDOG and clock monitor logic
n MICROWIRE/PLUS serial I/O
I/O Features
n Memory mapped I/O
n Software selectable I/O options (TRI-STATE® Output,
Push-Pull Output, Weak Pull Up Input, High Impedance
Input)
n Schmitt trigger inputs on ports G and L
n Package:
— 44 PLCC with 40 I/O pins
CPU/Instruction Set Features
n 1 µs instruction cycle time
n Twelve multi-source vectored interrupts servicing
— External Interrupt
— Idle Timer T0
— Three Timers (each with 2 Interrupts)
— MICROWIRE/PLUS
— Multi-Input Wake Up
— Software Trap
— Default VIS (default interrupt)
n Versatile and easy to use instruction set
n 8-bit Stack Pointer (SP) – stack in RAM
n Two 8-bit Register Indirect Data Memory Pointers (B
and X)
Fully Static CMOS
n Two power saving modes: HALT and IDLE
n Single supply operation: 2.5V to 5.5V
n Temperature range: −0˚C to +70˚C and −40˚C to +85˚C
Development Support
n Emulation and OTP devices
n Real time emulation and full program debug offered by
MetaLink Development System
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
MICROWIRE/PLUS™, COP8™, MICROWIRE™ and WATCHDOG™ are trademarks of National Semiconductor Corporation.
iceMASTER® is a registered trademark of MetaLink Corporation.
© 1999 National Semiconductor Corporation DS100076
www.national.com
1 page  
DC Electrical Characteristics (Continued)
−0˚C ≤ TA ≤ +70˚C unless otherwise specified
Parameter
Conditions
Min Typ
Max
Units
All others
3 mA
Maximum Input Current
Room Temp
±100
mA
without Latchup (Note 7) (Note 9)
RAM Retention Voltage, Vr
500 ns Rise
and Fall Time (min)
2
V
Input Capacitance
7 pF
Load Capacitance on D2
1000
pF
Note 2: tc = Instruction Cycle Time
Note 3: Maximum rate of voltage change must be < 0.5 V/ms.
Note 4: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC
and outputs driven low but not connected to a load.
Note 5: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations by bringing CKI high. Measurement of IDD HALT is done with device
neither sourcing nor sinking current; with L, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load;
all inputs tied to VCC; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up
CKI during HALT in crystal clock mode.
Note 6: The user must guarantee that D2 pin does not source more than 10 mA during RESET. If D2 sources more than 10 mA during reset, the device will go into
programming mode.
Note 7: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages VCC and the pins will have sink current to VCC when
biased at voltages VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins
will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD
transients.
Note 8: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 9: Parameter characterized but not tested.
AC Electrical Characteristics
−40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Conditions
Min Typ Max Units
Instruction Cycle Time (tc)
Crystal, Resonator,
R/C Oscillator
CKI Clock Duty Cycle (Note 9)
Rise Time (Note 9)
Fall Time (Note 9)
Inputs
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
fr = Max
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
1.0
3.0
40
DC µs
DC µs
60
5 ns
5 ns
tSETUP
tHOLD
Output Propagation Delay (Note 8)
tPD1, tPD0
SO, SK
All Others
MICROWIRE™ Setup Time (tUWS) (Note
9)
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
RL = 2.2k, CL = 100 pF
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
200
60
20
ns
ns
0.7 µs
1.0 µs
ns
MICROWIRE Hold Time (tUWH) (Note 9)
MICROWIRE Output Propagation Delay
(tUPD)
Input Pulse Width (Note 9)
56 ns
220 ns
Interrupt Input High Time
Interrupt Input Low Time
Timer 1, 2, 3 Input High Time
Timer 1, 2, 3 Input Low Time
Reset Pulse Width
1.0 tc
1.0 tc
1.0 tc
1.0 tc
1.0 µs
Note 10: tc = Instruction Cycle Time
Note 11: Maximum rate of voltage change must be < 0.5 V/ms.
5 www.national.com
5 Page 
Pin Descriptions
VCC and GND are the power supply pins. All VCC and GND
pins must be connected.
CKI is the clock input. This can come from an R/C generated
oscillator, or a crystal oscillator (in conjunction with CKO).
See Oscillator Description section.
RESET is the master reset input. See Reset Description sec-
tion.
The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently con-
figured as an input (Schmitt Trigger inputs on ports L and G),
output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also re-
served for the input pins of each I/O port. (See the memory
map for the various addresses associated with the I/O ports.)
Figure 4 shows the I/O port configurations. The DATA and
CONFIGURATION registers allow for each port bit to be in-
dividually configured under software control as shown below:
CONFIGURATION
DATA
Port Set-Up
Register
Register
0 0 Hi-Z Input
(TRI-STATE Output)
0 1 Input with Weak Pull-Up
1 0 Push-Pull Zero Output
1 1 Push-Pull One Output
PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
Port L supports Multi-Input Wake Up on all eight pins. L4 and
L5 are used for the timer input functions T2A and T2B. L6
and L7 are used for the timer input functions T3A and T3B.
Port L has the following alternate features:
L7 MIWU or T3B
L6 MIWU or T3A
L5 MIWU or T2B
L4 MIWU or T2A
L3 MIWU
L2 MIWU
L1 MIWU
L0 MIWU
Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input
pin (G6), and a dedicated output pin (G7). Pins G0 and
G2–G6 all have Schmitt Triggers on their inputs. Pin G1
serves as the dedicated WDOUT WATCHDOG output, while
pin G7 is either input or output depending on the oscillator
mask option selected. With the crystal oscillator option se-
lected, G7 serves as the dedicated output pin for the CKO
clock output. With the single-pin R/C oscillator mask option
selected, G7 serves as a general purpose input pin but is
also used to bring the device out of HALT mode with a low to
high transition on G7. There are two registers associated
with the G Port, a data register and a configuration register.
Therefore, each of the 5 I/O bits (G0, G2–G5) can be indi-
vidually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin (crystal clock option) or general purpose in-
put (R/C clock option), the associated bits in the data and
configuration registers for G6 and G7 are used for special
purpose functions as outlined on the next page. Reading the
G6 and G7 data bits will return zeros.
DS100076-5
FIGURE 4. I/O Port Configurations
Note that the chip will be placed in the HALT mode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register en-
ables the MICROWIRE/PLUS to operate with the alternate
phase of the SK clock. The G7 configuration bit, if set high,
enables the clock start up delay after HALT when the R/C
clock configuration is used.
Config Reg.
Data Reg.
G7 CLKDLY
HALT
G6 Alternate SK
IDLE
Port G has the following alternate features:
G6 SI (MICROWIRE Serial Data Input)
G5 SK (MICROWIRE Serial Clock)
G4 SO (MICROWIRE Serial Data Output)
G3 T1A (Timer T1 I/O)
G2 T1B (Timer T1 Capture Input)
G0 INTR (External Interrupt Input)
Port G has the following dedicated functions:
G7 CKO Oscillator dedicated output or general purpose
input
G1 WDOUT WATCHDOG and/or Clock Monitor dedi-
cated output
Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated pins
will return unpredicatable values.
Port I is an 8-bit Hi-Z input port, and also provides the analog
inputs to the A/D converter. The 28-pin device does not have
a full complement of Port I pins. The unavailable pins are not
terminated (i.e. they are floating). A read operation from
these unterminated pins will return unpredictable values.
The user should ensure that the software takes this into ac-
count by either masking out these inputs, or else restricting
the accesses to bit operations only. If unterminated, Port I
pins will draw power only when addressed.
11 www.national.com
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet COP988GD.PDF ] | |
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