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PDF COP942CJ Data sheet ( Hoja de datos )
| Número de pieza | COP942CJ | |
| Descripción | 8-Bit CMOS ROM Based Microcontrollers with 1k or 2k Memory/ Comparator and Brown Out Detector | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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September 1999
COP820CJ/COP840CJ Family
8-Bit CMOS ROM Based Microcontrollers with 1k or 2k
Memory, Comparator and Brown Out Detector
General Description
The COP820CJ/840CJ Family ROM based microcontrollers
are integrated COP8™ Base core devices with 1k or 2k
memory, an Analog comparator and Brownout detection.
These single-chip CMOS devices are suited for lower-
functionality applications where power and voltage fluctua-
tions are a consideration. Pin and software compatible (no
Brownout; different Vcc range) 4k/32k OTP versions are
available (COP87LxxCJ/RJ Family) for pre-production, and
for use with a range of COP8 software and hardware devel-
opment tools.
Family features include an 8-bit memory mapped architec-
ture, 10MHz CKI with 1us instruction cycle, one multi-
function 16-bit timer/counter, MICROWIRE/PLUS™ serial
I/O, one analog comparator, power saving HALT mode,
MIWU, on-chip R/C oscillator capacitor (COP840CJ), high
current outputs, software selectable I/O options, WATCH-
DOG™ timer, modulator/timer, Brownout detector, Power on
Reset, 2.5v-6.0v operation, and 16/20/28 pin packages.
In this datasheet, the term COP820CJ refers to packages in-
cluding the COP820CJ, COP822CJ, and COP823CJ; and
COP840CJ refers to COP840CJ, COP842CJ, COP940CJ,
and COP942CJ.
Devices included in this data sheet are:
Device
COP820CJ
COP822CJ
COP823CJ
COP840CJ
COP940CJ
COP842CJ
COP942CJ
Memory (bytes)
1k ROM
1k ROM
1k ROM
2k ROM
2k ROM
2k ROM
2k ROM
RAM (bytes)
64
54
64
128
128
128
128
I/O Pins
24
16
12
24
24
16
16
Packages
28 DIP/SOIC
20 DIP/SOIC
16 SOIC
28 DIP/SOIC
28 DIP/SOIC
20 DIP/SOIC
20 DIP/SOIC
Temperature
-40 to +85˚C
-40 to +85˚C
-40 to +85˚C
-40 to +85˚C
-0 to +70˚C
-40 to +85˚C
-0 to +70˚C
Comments
Low EMI
2.5V-4.5V, CJH = 4V-6V
2.5V-4.5V, CJH = 4V-6V
Key Features
n Multi-Input Wake Up (on the 8-bit Port L)
n Brown out detector
n Analog comparator
n Modulator/timer (High speed PWM for IR transmission)
n 16-bit multi-function timer supporting
— PWM mode
— External event counter mode
— Input capture mode
n 1024 or 2048 bytes of ROM
n 64 or 128 bytes of RAM
n Quiet design (low radiated emissions)
n Integrated capacitor for the R/C oscillator for COP840CJ
I/O Features
n Software selectable I/O options (TRI-STATE® output,
push-pull output, weak pull-up input, high impedance
input)
n High current outputs (8 pins)
n Packages
— 16 SO with 12 I/O pins for COP820CJ
— 20 DIP/SO with 16 I/O pins
— 28 DIP/SO with 24 I/O pins
n Schmitt trigger inputs on Port G
n MICROWIRE/PLUS serial I/O
CPU/Instruction Set Feature
n 1 µs instruction cycle time
n Three multi-source vectored interrupts servicing
— External interrupt with selectable edge
— Timer interrupt
— Software interrupt
n 8-bit Stack Pointer (SP) — stack in RAM
n Two 8-bit register indirect data memory pointers (B, X)
Fully Static CMOS
n Low current drain (typically < 1 µA)
n Single supply operation: 2.5V to 6.0V
n Temperature ranges: −0˚C to +70˚C and −40˚C to +85˚C
Development Support
n Emulation and OTP devices
n Real time emulation and full program debug offered by
MetaLink Development System
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
COP8™, MICROWIRE™, MICROWIRE/PLUS™ and WATCHDOG™ are trademarks of National Semiconductor Corporation.
iceMASTER® is a registered trademark of MetaLink Corporation.
© 2000 National Semiconductor Corporation DS011208
www.national.com
1 page  
DC Electrical Characteristics (Continued)
−0˚C ≤ TA ≤ + 70˚C for COP94x and −40˚C ≤ TA ≤ +85˚C for all others
Parameter
Conditions
Output Current Levels
D Outputs:
Source
Sink
L4–L7 Output Sink
All Others
VCC = 4.5V, VOH = 3.8V
VCC = 2.5V, VOH = 1.8V
VCC = 4.5V, VOL = 1.0V
VCC = 2.5V, VOH = 0.4V
VCC = 4.5V, VOL = 2.5V
Source (Weak Pull-up Mode)
Source (Push-pull Mode)
Sink (Push-pull Mode)
TRI-STATE Leakage
VCC = 4.5V, VOH = 3.2V
VCC = 2.5V, VOH = 1.8V
VCC = 4.5V, VOH = 3.8V
VCC = 2.5V, VOH = 1.8V
VCC = 4.5V, VOL = 0.4V
VCC = 2.5V, VOL = 0.4V
Allowable Sink/Source
Current Per Pin
D Outputs
L4–L7 (Sink)
All Others
Maximum Input Current
Room Temperature
without Latchup (Note 5)
RAM Retention Voltage, Vr
500 ns Rise and
Fall Time (Min)
Input Capacitance
Load Capacitance on D2
Min Typ Max Units
−0.4
−0.2
10
2
15
−10
−2.5
−0.4
−0.2
1.6
0.7
−2.0
−110
−33
+2.0
mA
mA
mA
mA
mA
µA
µA
mA
mA
mA
mA
µA
15
20
3
±100
mA
mA
mA
mA
2.0 V
7
1000
pF
pF
Note 2: Rate of voltage change must be less than 10 V/mS.
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. HALT test conditions: L, and G0..G5 ports configured as outputs and set
high. The D port set to zero. All inputs tied to VCC. The comparator and the Brown Out circuits are disabled.
Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than VCC and the pins will have sink current
to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω
(typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
5 www.national.com
5 Page 
Memory (Continued)
mapped as “registers”, these can be loaded immediately,
decremented and tested. Three specific registers: X, B, and
SP are mapped into this space, the other registers are avail-
able for general usage.
Any bit of data memory can be directly set, reset or tested.
All I/O and registers (except A and PC) are memory mapped;
therefore, I/O bits and register bits can be directly and indi-
vidually set, reset and tested, except the write once only bit
(WDREN, WATCHDOG Reset Enable), and the unused and
read only bits in CNTRL2 and WDREG registers.
Note: RAM contents are undefined upon power-up.
Reset
EXTERNAL RESET
The RESET input pin when pulled low initializes the
micro-controller. The user must insure that the RESET pin is
held low until VCC is within the specified voltage range and
the clock is stabilized. An R/C circuit with a delay 5x greater
than the power supply rise time is recommended (Figure 4).
The device immediately goes into reset state when the RE-
SET input goes low. When the RESET pin goes high the de-
vice comes out of reset state synchronously. The device will
be running within two instruction cycles of the RESET pin go-
ing high. The following actions occur upon reset:
Port L
TRI-STATE
Port G
TRI-STATE
Port D
HIGH
PC CLEARED
RAM Contents
RANDOM with Power-On-
Reset
UNAFFECTED with external
Reset (power already applied)
B, X, SP
Same as RAM
PSW, CNTRL1,
CNTRL2
and WDREG Reg.
CLEARED
Multi-Input Wakeup
Reg.
WKEDG, WKEN
CLEARED
WKPND
UNKNOWN
Data and Configuration
Registers for L & G
CLEARED
WATCHDOG Timer
Prescaler/Counter each
loaded with FF
The device comes out of the HALT mode when the RESET
pin is pulled low. In this case, the user has to ensure that the
RESET signal is low long enough to allow the oscillator to re-
start. An internal 256 tc delay is normally used in conjunction
with the two pin crystal oscillator. When the device comes
out of the HALT mode through Multi-Input Wakeup, this de-
lay allows the oscillator to stabilize.
The following additional actions occur after the device
comes out of the HALT mode through the RESET pin.
If a two pin crystal/resonator oscillator is being used:
RAM Contents
UNCHANGED
Timer T1 and A Contents
UNKNOWN
WATCHDOG Timer Prescaler/Counter ALTERED
If the external or RC Clock option is being used:
RAM Contents
UNCHANGED
Timer T1 and A Contents
UNCHANGED
WATCHDOG Timer Prescaler/Counter ALTERED
The external RESET takes priority over the Brown Out Re-
set.
Note: If the RESET pin is pulled low while Brown Out occurs (Brown Out cir-
cuit has detected Brown Out condition), the external reset will not oc-
cur until the Brown Out condition is removed. External reset has prior-
ity only if VCC is greater than the Brown Out voltage.
RC > 5 x Power Supply Rise Time
DS011208-51
FIGURE 4. Recommended Reset Circuit
WATCHDOG RESET
With WATCHDOG enabled, the WATCHDOG logic resets
the device if the user program does not service the WATCH-
DOG timer within the selected service window. The WATCH-
DOG reset does not disable the WATCHDOG. Upon
WATCHDOG reset, the WATCHDOG Prescaler and Counter
are each initialized with FF Hex.
The following actions occur upon WATCHDOG reset that are
different from external reset.
WDREN WATCHDOG Reset Enable bit UNCHANGED
WDUDFWATCHDOG Underflow bitUNCHANGED
Additional initialization actions that occur as a result of
WATCHDOG reset are as follows:
Port L
Port G
Port D
PC
RAM Contents
B, X, SP
PSW, CNTRL1 and
CNTRL2 (except WDUDF
Bit) Registers
Multi-Input Wakeup
Registers
WKEDG, WKEN
WKPND
Data and Configuration
Registers for L & G
WATCHDOG Timer
TRI-STATE
TRI-STATE
HIGH
CLEARED
UNCHANGED/RANDOM
UNCHANGED
CLEARED
CLEARED
UNKNOWN
CLEARED
Prescalar/Counter
each loaded with FF
11 www.national.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet COP942CJ.PDF ] | |
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