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PDF COP888GW Data sheet ( Hoja de datos )
| Número de pieza | COP888GW | |
| Descripción | 8-Bit Microcontroller with Pulse Train Generators | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
September 1996
COP888GW
8-Bit Microcontroller with Pulse Train Generators
and Capture Modules
General Description
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconduc-
tor’s M2CMOSTM process technology The COP888GW is a
member of this expandable 8-bit core processor family of
microcontrollers It is a fully static part fabricated using dou-
ble-metal silicon gate microCMOS technology
Features include an 8-bit memory mapped architecture MI-
CROWIRE PLUS serial I O two 16-bit timer counters sup-
porting three modes (Processor Independent PWM genera-
tion External Event counter and Input Capture mode capa-
bilities) four independent 16-bit pulse train generators with
16-bit prescalers two independent 16-bit input capture
modules with 8-bit prescalers multiply and divide functions
full duplex UART and two power savings modes (HALT and
IDLE) both with a multi-sourced wake up interrupt capabili-
ty This multi-sourced interrupt capability may also be used
independent of the HALT or IDLE modes
Each I O pin has software selectable configurations The
devices operate over a voltage range of 2 5V–6V High
throughput is achieved with an efficient regular instruction
set operating at a maximum of 1 ms per instruction rate The
device has low EMI emissions Low radiated emissions are
achieved by gradual turn-on output drivers and internal ICC
filters on the chip logic and crystal oscillator The device is
available in 68-pin PLCC package
Key Features
Y Two 16-bit input capture modules with 8-bit prescalers
Y Four Pulse Train Generators with 16-bit prescalers
Y Full duplex UART
Y Two 16-bit timers each with two 16-bit registers
supporting
Processor independent PWM mode
External event counter mode
Input capture mode
Y Quiet design (low radiated emissions)
Y 16 kbytes on-board ROM
Y 512 bytes on-board RAM
Additional Peripheral Features
Y Idle Timer
Y Multi-Input Wake-Up (MIWU) with optional interrupts (8)
Y MICROWIRE PLUSTM serial I O
I O Features
Y Memory mapped I O
Y Software selectable I O options (TRI-STATE Output
Push-Pull Output Weak Pull-Up Input High Impedance
Input)
Y Schmitt trigger inputs on port G
Y Package 68-pin PLCC
CPU Instruction Set Features
Y 1 ms instruction cycle time
Y Fourteen multi-source vectored interrupts servicing
External Interrupt with selectable edge
Idle Timer T0
Two Timers (each with 2 interrupts)
MICROWIRE PLUS
Multi-Input Wake-Up
Software Trap
UART (2)
Capture Timers
Counters (one vector for all four counters)
Default VIS (default interrupt)
Y Versatile and easy-to-use instruction set
Y 8-bit Stack Pointer SP (stack in RAM)
Y Two 8-bit register indirect data memory pointers
(B and X)
Fully Static CMOS
Y Two power saving modes HALT and IDLE
Y Low current drain (typically k1 mA)
Y Single supply operation 2 5V – 5 5V
Y Temperature range b40 C to a85 C
Development Support
Y Emulation and OTP device
Y Real time emulation and full program debug offered by
MetaLink’s Development System
TRI-STATE is a registered trademark of National Semiconductor Corporation
M2CMOSTM MICROWIRE PLUSTM COPSTM MICROWIRETM and WATCHDOGTM are trademarks of National Semiconductor Corporation
IBM PC PC-AT and PC XT are registered trademarks of International Business Machines Corporation
iceMASTERTM is a trademark of MetaLink Corporation
C1996 National Semiconductor Corporation TL DD12065
RRD-B30M106 Printed in U S A
http www national com
1 page  
Typical Performance Characteristics b40 C s TA s a85 C
Port D Source Current
Port D Sink Current
TL DD 12065 – 23
Ports C G L E F Source Current
TL DD 12065 – 24
Ports C G L E F Sink Current
TL DD 12065 – 25
Ports C G L E F Weak Pull-Up Source Current
TL DD 12065 – 26
Dynamic IDD vs VCC
Idle IDD vs VCC
TL DD 12065 – 27
HALT IDD vs VCC
TL DD 12065 – 28
TL DD 12065 – 29
5
TL DD 12065 – 30
http www national com
5 Page 
Timers
The device contains a very versatile set of timers (T0 T1
T2) All timers and associated autoreload capture registers
power up containing random data
TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
reaI time and Iow power with the IDLE mode This IDLE
mode support is furnished by the IDLE timer T0 which is a
16-bit timer The Timer T0 runs continuously at the fixed
rate of the instruction cycle cIock tc The user cannot read
or write to the IDLE Timer T0 which is a count down timer
The Timer T0 supports the following functions
Exit out of the Idle Mode (See Idle Mode description)
Start up delay out of the HALT mode
The IDLE Timer T0 can generate an interrupt when the thir-
teenth bit toggIes This toggle is Iatched into the T0PND
pending flag and wiIl occur every 4 ms at the maximum
clock frequency (tc e 1 ms) A control flag T0EN allows the
interrupt from the thirteenth bit of Timer T0 to be enabled or
disabIed Setting T0EN will enable the interrupt while reset-
ting it will disable the interrupt
TIMER T1 AND TIMER T2
The device has a set of two powerful timer counter blocks
T1 and T2 The associated features and functioning of a
timer block are described by referring to the timer block Tx
Since the two timer blocks T1 and T2 are identical all com-
ments are equally applicable to either of the two timer
blocks
Each timer block consists of a 16-bit timer Tx and two
supporting 16-bit autoreload capture registers RxA and
RxB Each timer block has two pins associated with it TxA
and TxB The pin TxA supports I O required by the timer
block while the pin TxB is an input to the timer block The
powerful and flexible timer block allows the device to easily
perform all timer functions with minimal software overhead
The timer block has three operating modes Processor Inde-
pendent PWM mode External Event Counter mode and
Input Capture mode
The control bits TxC3 TxC2 and TxC1 allow selection of
the different modes of operation
Mode 1 Processor Independent PWM Mode
As the name suggests this mode allows the device to gen-
erate a PWM signal with very minimal user intervention The
user only has to define the parameters of the PWM signal
(ON time and OFF time) Once begun the timer block will
continuously generate the PWM signal completely indepen-
dent of the microcontroller The user software services the
timer block only when the PWM parameters require updat-
ing
In this mode the timer Tx counts down at a fixed rate of tc
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers RxA and RxB The very
first underflow of the timer causes the timer to reload from
the register RxA Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB
The Tx Timer control bits TxC3 TxC2 and TxC1 set up the
timer for PWM mode operation
Figure 7 shows a block diagram of the timer in PWM mode
The underfIows can be programmed to toggle the TxA out-
put pin The underfIows can also be programmed to gener-
ate interrupts
UnderfIows from the timer are alternately latched into two
pending flags TxPNDA and TxPNDB The user must reset
these pending fIags under software control Two control en-
abIe fIags TxENA and TxENB alIow the interrupts from the
timer underflow to be enabled or disabled Setting the timer
enable flag TxENA wilI cause an interrupt when a timer un-
derflow causes the RxA register to be reloaded into the tim-
er Setting the timer enable flag TxENB will cause an inter-
rupt when a timer underflow causes the RxB register to be
reloaded into the timer Resetting the timer enable flags will
disable the associated interrupts
Either or both of the timer underflow interrupts may be en-
abled This gives the user the flexibility of interrupting once
per PWM period on either the rising or falling edge of the
PWM output Alternatively the user may choose to interrupt
on both edges of the PWM output
Mode 2 ExternaI Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above The main difference is that
the timer Tx is cIocked by the input signal from the TxA pin
The Tx timer control bits TxC3 TxC2 and TxC1 allow the
timer to be clocked either on a positive or negative edge
from the TxA pin Underflows from the timer are Iatched into
the TxPNDA pending flag Setting the TxENA control flag
will cause an interrupt when the timer underflows
FIGURE 7 Timer in PWM Mode
11
TL DD 12065 – 8
http www national com
11 Page | ||
| Páginas | Total 44 Páginas | |
| PDF Descargar | [ Datasheet COP888GW.PDF ] | |
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