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PDF COP87L88RK Data sheet ( Hoja de datos )
| Número de pieza | COP87L88RK | |
| Descripción | 8-Bit CMOS OTP Microcontrollers with 8k or 32k Memory/ Comparator/ and Single-slope A/D Capability | |
| Fabricantes | National Semiconductor | |
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September 1999
COP87L88EK/RK Family
8-Bit CMOS OTP Microcontrollers with 8k or 32k
Memory, Comparator, and Single-slope A/D Capability
General Description
The COP87L88EK/RK Family OTP (One Time Program-
mable) microcontrollers are highly integrated COP8™ Fea-
ture core devices with 16k or 32k memory and advanced
features including a Multi-Input Comparator and
Single-slope A/D capability. These multi-chip CMOS devices
are suited for applications requiring a full featured, low EMI
controller with an analog comparator, current source, and
voltage reference, and as pre-production devices for a
masked ROM design. Lower cost pin and software compat-
ible 8k ROM versions (COP888EK) are available for use with
a range of COP8 software and hardware development tools.
Family features include an 8-bit memory mapped architec-
ture, 10 MHz CKI (-XE = crystal oscillator) with 1 µs instruc-
tion cycle, three multi-function 16-bit timer/counters with
PWM, MICROWIRE/PLUS™ serial I/O, one analog com-
parator with seven input multiplexor, an analog current
source and VCC/2 reference, two power saving HALT/IDLE
modes, idle timer, MIWU, high current outputs, software se-
lectable I/O options, WATCHDOG™ timer and Clock Monitor,
2.7V to 5.5V operation and 28/40/44 pin packages.
Devices included in this datasheet are:
Device
COP87L84EK
COP87L88EK
COP87L84RK
COP87L88RK
Memory (bytes)
16k OTP EPROM
16k OTP EPROM
32k OTP EPROM
32k OTP EPROM
RAM (bytes)
256
256
256
256
I/O Pins
24
36/40
24
36/40
Packages
28 DIP/SOIC
40 DIP, 44 PLCC
28 DIP/SOIC
40 DIP, 44 PLCC
Temperature
-40 to +85˚C
-40 to +85˚C
-40 to +85˚C
-40 to +85˚C
Key Features
DataSheent4SUch.mciottmtrigger inputs on Port G and L
n Analog function block with
— Analog comparator with seven input multiplexor
CPU/Instruction Set Feature
— Constant current source and VCC/2 reference
n Three 16-bit timers, each with two 16-bit registers
supporting:
— Processor Independent PWM mode
n 1 µs instruction cycle time
n Twelve multi-source vectored interrupts servicing
— External Interrupt with selectable edge
— Idle Timer T0
— External Event counter mode
— Three Timers (Each with 2 interrupts)
— Input Capture mode
— MICROWIRE/PLUS
n 8 or 32 kbytes on-board EPROM with security feature
n 256 bytes on-board RAM
— Multi-Input Wake Up
— Software Trap
— Default VIS (default interrupt)
Additional Peripheral Features
n Idle Timer
n Multi-Input Wake Up (MIWU) with optional interrupts (8)
n WATCHDOG and Clock Monitor logic
n Versatile and easy to use instruction set
n 8-bit Stack Pointer (SP) — stack in RAM
n Two 8-bit Register Indirect Data Memory Pointers
(B, X)
n MICROWIRE/PLUS serial I/O
Fully Static CMOS
I/O Features
n Software selectable I/O options ( TRI-STATE™Output,
Push-Pull Output, Weak Pull-Up Input, High Impedance
Input)
n Packages:
— 44 PLCC with 40 I/O pins
— 40 DIP with 36 I/O pins
— 28 DIP/SO with 24 I/O pins
n Two power saving modes: HALT and IDLE
n Single supply operation: 2.7V to 5.5V
n Temperature ranges: −40˚C to +85˚C
Development Support
n Emulation devices for the COP888EK/COP884EK
n Real time emulation and full program debug offered by
MetaLink Development System
COP8™ is a trademark of National Semiconductor Corporation.
MICROWIRE/PLUS™ is a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
WATCHDOG™ is a trademark of National Semiconductor Corporation.
iceMASTER™ is a trademark of MetaLink Corporation.
© 1999 National Semiconductor Corporation DS101133
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
Voltage at Any Pin
7V
−0.3V to VCC + 0.3V
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
100 mA
110 mA
Storage Temperature Range
−65˚C to +140˚C
Note 1: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
DC Electrical Characteristics
−40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Conditions
Min Typ Max
Operating Voltage
2.7 5.5
Power Supply Ripple (Note 3)
Supply Current (Note 4)
Peak-to-Peak
0.1 VCC
CKI = 10 MHz
CKI = 4 MHz
HALT Current (Note 5)
IDLE Current (Note 4)
VCC = 5.5V, tc = 1 µs
VCC = 4.0V, tc = 2.5 µs
VCC = 5.5V, CKI = 0 MHz
VCC = 4.0V, CKI = 0 MHz
16.5
6.5
12
8
CKI = 10 MHz
CKI = 4 MHz
Input Levels (VIH, VIL)
RESET
VCC = 5.5V, tc = 1 µs
VCC = 4.0V, tc = 10 µs
3.5
0.7
Logic High
Logic Low
CKI, All Other Inputs
0.8 VCC
0.2 VCC
Logic High
Logic Low
Hi-Z Input Leakage
Input Pullup Current
G and L Port Input Hysteresis (Note 8)
Output Current Levels
0.7 VCC
DataSheet4U.com
VCC = 5.5V
VCC = 5.5V, VIN = 0V
−2
−40
0.2 VCC
+2
−250
0.35 VCC
D Outputs
Source
Sink
All Others
VCC = 4.5V, VOH = 3.3V
VCC = 4.5V, VOL = 1V
−0.4
10
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
Allowable Sink/Source Current per Pin
VCC = 4.5V, VOH = 2.7V
VCC = 4.5V, VOH = 3.3V
VCC = 4.5V, VOL = 0.4V
VCC = 6.0V
−10
−0.4
1.6
−2
−110
+2
(Note 8)
D Outputs (Sink)
15
All others
3
Maximum Input Current
Room Temp
±200
without Latchup (Note 6)
RAM Retention Voltage, Vr
500 ns Rise
and Fall Time (min)
2
Input Capacitance
7
Load Capacitance on D2
1000
Units
V
V
mA
mA
µA
µA
mA
mA
V
V
V
V
µA
µA
V
mA
mA
µA
mA
mA
µA
mA
mA
mA
V
pF
pF
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Functional Description (Continued)
Data Memory Segment RAM
S is the 8-bit Data Segment Address Register used to extend
Extension
the lower half of the address range (00 to 7F) into 256 data
segments of 128 bytes each.
Data memory address 0FF is used as a memory mapped lo-
cation for the Data Segment Address Register (S).
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC).
The data store memory is either addressed directly by a
single byte address within the instruction, or indirectly rela-
The device can be configured to inhibit external reads of the
tive to the reference of the B, X, or SP pointers (each con-
program memory. This is done by programming the Security
tains a single-byte address). This single-byte address allows
Byte.
an addressing range of 256 locations from 00 to FF hex. The
upper bit of this single-byte address divides the data store
PROGRAM MEMORY
memory into two separate sections as outlined previously.
The program memory consists of 8192 bytes of OTP
EPROM. These bytes may hold program instructions or con-
stant data (data tables for the LAID instruction, jump vectors
for the JID instruction, and interrupt vectors for the VIS in-
struction). The program memory is addressed by the 15-bit
program counter (PC). All interrupts in the devices vector to
program memory location 0FF Hex.
The device can be configured to inhibit external reads of the
program memory. This is done by programming the Security
Byte.
With the exception of the RAM register memory from ad-
dress locations 00F0 to 00FF, all RAM memory is memory
mapped with the upper bit of the single-byte address being
equal to zero. This allows the upper bit of the single-byte ad-
dress to determine whether or not the base address range
(from 0000 to 00FF) is extended. If this upper bit equals one
(representing address range 0080 to 00FF), then address
extension does not take place. Alternatively, if this upper bit
equals zero, then the data segment extension register S is
used to extend the base address range (from 0000 to 007F)
from XX00 to XX7F, where XX represents the 8 bits from the
SECURITY FEATURE
S register. Thus the 128-byte data segment extensions are
located from addresses 0100 to 017F for data segment 1,
The program memory array has an associate Security Byte
0200 to 027F for data segment 2, etc., up to FF00 to FF7F
that is located outside of the program address range. This
for data segment 255. The base address range from 0000 to
byte can be addressed only from programming mode by a
007F represents data segment 0.
programmer tool.
Figure 5 illustrates how the S register data memory exten-
Security is an optional feature and can only be asserted after
sion is used in extending the lower half of the base address
the memory array has been programmed and verified. A se-
range (00 to 7F hex) into 256 data segments of 128 bytes
cured part will read all 00(hex) by a programmer. The part
each, with a total addressing range of 32 kbytes from XX00
will fail Blank Check and will fail Verify operations. A Read
to XX7F. This organization allows a total of 256 data seg-
operation will fill the programmer’s memory with 00(hDexa).taShemeetn4tsUo.fc1o28mbytes each with an additional upper base seg-
The Security Byte itself is always readable with value of
ment of 128 bytes. Furthermore, all addressing modes are
00(hex) if unsecure and FF(hex) if secure.
available for all data segments. The S register must be
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X, SP pointers and S register.
The data memory consists of 256 bytes of RAM. Sixteen
bytes of RAM are mapped as “registers” at addresses 0F0 to
0FF Hex. These registers can be loaded immediately, and
also decremented and tested with the DRSZ (decrement
register and skip if zero) instruction. The memory pointer
registers X, SP, B and S are memory mapped into this space
at address locations 0FC to 0FF Hex respectively, with the
other registers being available for general usage.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumula-
tor (A) bits can also be directly and individually tested.
changed under program control to move from one data seg-
ment (128 bytes) to another. However, the upper base seg-
ment (containing the 16 memory registers, I/O registers,
control registers, etc.) is always available regardless of the
contents of the S register, since the upper base segment
(address range 0080 to 00FF) is independent of data seg-
ment extension.
The instructions that utilize the stack pointer (SP) always ref-
erence the stack as part of the base segment (Segment 0),
regardless of the contents of the S register. The S register is
not changed by these instructions. Consequently, the stack
(used with subroutine linkage and interrupts) is always lo-
cated in the base segment. The stack pointer will be intitial-
ized to point at data memory location 006F as a result of re-
set.
The 128 bytes of RAM contained in the base segment are
split between the lower and upper base segments. The first
112 bytes of RAM are resident from address 0000 to 006F in
the lower base segment, while the remaining 16 bytes of
RAM represent the 16 data memory registers located at ad-
dresses 00F0 to 00FF of the upper base segment. No RAM
is located at the upper sixteen addresses (0070 to 007F) of
Note: RAM contents are undefined upon power-up.
the lower base segment.
Additional RAM beyond these initial 128 bytes, however, will
always be memory mapped in groups of 128 bytes (or less)
at the data segment address extensions (XX00 to XX7F) of
the lower base segment. The additional 128 bytes of RAM
are memory mapped at address locations 0100 to 017F hex.
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| Páginas | Total 41 Páginas | |
| PDF Descargar | [ Datasheet COP87L88RK.PDF ] | |
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