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PDF LT3030 Data sheet ( Hoja de datos )
| Número de pieza | LT3030 | |
| Descripción | Micropower Linear Regulator | |
| Fabricantes | Linear | |
| Logotipo |  |
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LT3030
Dual 750mA/250mA
Low Dropout, Low Noise,
Micropower Linear Regulator
Features
Description
n Output Current: 750mA/250mA
n Low Dropout Voltage: 300mV
n Low Noise: 20μVRMS (10Hz to 100kHz)
n Low Quiescent Current: 120μA/75μA
n Wide Input Voltage Range: 1.7V to 20V
n Adjustable Output: 1.220V Reference Voltage
n Shutdown Quiescent Current: <1μA
n Stable with 10µF/3.3µF Minimum Output Capacitor
n Stable with Ceramic, Tantalum or Aluminum
Electrolytic Capacitors
n Precision Threshold for Shutdown Logic or UVLO Function
n PWRGD Flag for each Output
n Reverse Battery and Reverse Output-to-Input
Protection
n Current Limit with Foldback and Thermal Shutdown
n Thermally Enhanced 20-Lead TSSOP and
28-Lead (4mm × 5mm) QFN Packages
Applications
n General Purpose Linear Regulator
n Battery-Powered Systems
n Microprocessor Core/Logic Supplies
n Post Regulator for Switching Supplies
n Tracking/Sequencing Power Supplies
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
The LT®3030 is a dual, micropower, low noise, low dropout
linear regulator. The device operates with either common
or independent input supplies for each channel, over a
1.7V to 20V input voltage range. Output 1/Output 2 supply
750mA/250mA respectively with a typical dropout voltage
of 300mV. With an external 10nF bypass capacitor, output
noise is only 20μVRMS over a 10Hz to 100kHz bandwidth.
Designed for use in battery-powered systems, the low
120μA/75μA quiescent current makes it an ideal choice.
In shutdown, quiescent current drops to less than 1μA.
Shutdown control is independent for each channel and
its precision logic threshold allows for voltage lockout
functionality. The LT3030 includes a PWRGD flag for each
channel to indicate output regulation.
The LT3030 optimizes stability and transient response with
low ESR ceramic output capacitors, requiring a minimum
of only 10μF/3.3μF.
Internal circuitry provides reverse-battery protection,
reverse-current protection, current limiting with foldback
and thermal shutdown with hysteresis. The adjustable
output voltage device has a 1.220V reference voltage.
The LT3030 is offered in the thermally enhanced 20-lead
TSSOP and 28-lead, low profile (4mm × 5mm × 0.75mm)
QFN packages.
Typical Application
2.5VIN to 1.8V/1.5V Application
VIN
2.5V
3.3µF
IN1 OUT1
IN2 LT3030
SHDN1
BYP1
10nF
113k
1%
1M 1M
SHDN2
PWRGD1
ADJ1
237k
1%
PWRGD2
OUT2
BYP2
10nF
54.9k
1%
GND
ADJ2
3030 TA01a
237k
1%
10µF
VOUT1
1.8V
750mA
3.3µF
VOUT2
1.5V
250mA
For more information www.linear.com/LT3030
Dropout Voltage vs Load Current
500
450 TJ = 25°C
400
350
300 OUT2
250
200 OUT1
150
100
50
0
0 75 150 225 300 375 450 525 600 675 750
OUTPUT CURRENT (mA)
3030 TA01b
3030fa
1
1 page  
LT3030
Typical Performance Characteristics TJ = 25°C, unless otherwise noted.
OUT1 Typical Dropout Voltage
500
450
400
350 TJ = 125°C
TJ = 150°C
300 TJ = 25°C
250
200
150 TJ = –55°C
100
50
0
0 75 150 225 300 375 450 525 600 675 750
OUTPUT CURRENT (mA)
3030 G01
OUT2 Typical Dropout Voltage
500
450
400
350
TJ = 125°C
TJ = 150°C
300 TJ = 25°C
250
200
150 TJ = –55°C
100
50
0
0 25 50 75 100 125 150 175 200 225 250
OUTPUT CURRENT (mA)
3030 G04
OUT1 Guaranteed Dropout
Voltage
500
= TEST POINTS
450
400 TJ = 150°C
350
300 TJ = 25°C
250
200
150
100
50
0
0 75 150 225 300 375 450 525 600 675 750
OUTPUT CURRENT (mA)
3030 G02
OUT2 Guaranteed Dropout
Voltage
500
= TEST POINTS
450
TJ = 150°C
400
350 TJ = 25°C
300
250
200
150
100
50
0
0 25 50 75 100 125 150 175 200 225 250
OUTPUT CURRENT (mA)
3030 G05
OUT1 Dropout Voltage
vs Temperature
500
450
IL = 750mA
IL = 500mA
400
IL = 300mA
IL = 100mA
350 IL = 10mA
300 IL = 1mA
250
200
150
100
50
0
–75 –50 –25
0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3030 G03
OUT2 Dropout Voltage
vs Temperature
500
450
IL = 250mA
IL = 175mA
400
IL = 100mA
IL = 50mA
350 IL = 10mA
300 IL = 1mA
250
200
150
100
50
0
–75 –50 –25
0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3030 G06
Quiescent Current
300
VIN1 = VIN2 = 6V
250 RL1 = RL2 = 243k; IL1 = IL2 = 5µA
200
OUTPUT 1
150 VSHDN1 = VIN1
100
OUTPUT 2
50 VSHDN2 = VIN2
0
–75 –50 –25
0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3030 G07
ADJ1/ADJ2 Pin Voltage
1.244
IL1 = IL2 = 1mA
1.238
1.232
1.226
ADJ2
1.220
1.214
ADJ1
1.208
1.202
1.196
–75 –50 –25
0 25 50 75 100 125 150 175
TEMPERATURE (°C)
3030 G08
For more information www.linear.com/LT3030
Quiescent Current
300
TJ = 25°C
250
RL1 = RL2 = 243k; IL1 = IL2 = 5µA
VOUT1 = VOUT2 = 1.220V
200
150 OUTPUT 1, VSHDN1 = VIN1
100 OUTPUT 2, VSHDN2 = VIN2
50
OUTPUT 1; VSHDN1 = 0V
0 OUTPUT 2; VSHDN2 = 0V
0 2 4 6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)
3030 G09
3030fa
5
5 Page 
LT3030
Pin Functions (QFN/TSSOP)
OUT1, OUT2 (Pins 1, 2, 7, 8/Pins 3, 4, 7, 8): Output. The
OUT1/OUT2 pins supply power to the loads. A minimum
10μF/3.3μF output capacitor prevents oscillations on
OUT1/OUT2. Applications with large output load transients
require larger values of output capacitance to limit peak
voltage transients. See the Applications Information sec-
tion for more on output capacitance and on reverse output
characteristics.
GND (Pins 3, 4, 5, 6, 11, 12, 13, 18, 19, 24, 25, 26,
Exposed Pad Pin 29/Pins 5, 6, 15, 16, Exposed Pad Pin
21): Ground. The exposed pad (backside) of the QFN and
TSSOP packages is an electrical connection to GND. To
ensure proper electrical and thermal performance, sol-
der the exposed pad to the PCB ground and tie directly
to GND pins. Connect the bottom of the output voltage
setting resistor divider directly to GND for optimum load
regulation performance.
IN1, IN2 (Pins 20, 21, 16, 17/Pins 17, 18, 13, 14): In-
put. The IN1/IN2 pins supply power to each channel. The
LT3030 requires a bypass capacitor at the IN1/IN2 pins
if located more than six inches away from the main input
filter capacitor. Include a bypass capacitor in battery-
powered circuits, as a battery’s output impedance rises
with frequency. A bypass capacitor in the range of 1μF to
10μF suffices. The LT3030’s design withstands reverse
voltages on the IN pins with respect to ground and the
OUT pins. In the case of a reversed input, which occurs
if a battery is plugged in backwards, the LT3030 acts as
if a diode is in series with its input. No reverse current
flows into the LT3030 and no reverse voltage appears at
the load. The device protects itself and the load.
PWRGD1, PWRGD2 (Pins 22, 15/Pins 19, 12): Power
Good. The PWRGD flag is an open-collector flag to indicate
that the output voltage has increased above 90% of the
nominal output voltage. There is no internal pull-up on
this pin; a pull-up resistor must be used. The PWRGD pin
changes state from an open-collector pull-down to high
impedance after the output increases above 90% of the
nominal voltage. The maximum pull-down current of the
PWRGD pin in the low state is 100μA.
SHDN1, SHDN2 (Pins 23, 14/Pins 20, 11): Shutdown.
Pulling the SHDN1 or SHDN2 pin low puts its correspond-
ing LT3030 channel into a low power state and turns its
output off. The SHDN1 and SHDN2 pins are completely
independent of each other, and each SHDN pin only affects
operation on its corresponding channel. Drive the SHDN1
and SHDN2 pins with either logic or an open collector/drain
with pull-up resistors. The resistors supply the pull-up
current to the open collectors/drains and the SHDN1 or
SHDN2 current, typically less than 1μA. If unused, con-
nect SHDN1 and SHDN2 to their corresponding IN pins.
Each channel will be in its low power shutdown state if its
corresponding SHDN pin is not connected.
ADJ1, ADJ2 (Pins 27, 10/Pins 1, 10): Adjust Pin. These
are the error amplifier inputs. These pins are internally
clamped to ±9V. A typical input bias current of 30nA flows
into the pins (see curve of ADJ1/ADJ2 Pin Bias Current vs
Temperature in the Typical Performance Characteristics
section). The ADJ1 and ADJ2 pin voltages are 1.220V
referenced to ground and the output voltage range is
1.220V to 19.5V.
BYP1, BYP2 (Pins 28, 9/Pins 2, 9): Bypass. Connecting
a capacitor between OUT and BYP of a respective chan-
nel bypasses the LT3030 reference to achieve low noise
performance, improve transient response and soft-start
the output. Internal circuitry clamps the BYP1/BYP2 pins
to ±0.6V (one VBE) from ground. A small capacitor from
the corresponding output to this pin bypasses the refer-
ence to lower the output voltage noise. Using a maximum
value of 10nF reduces the output voltage noise to a typical
20μVRMS over a 10Hz to 100kHz bandwidth. If not used,
this pin must be left unconnected.
For more information www.linear.com/LT3030
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11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet LT3030.PDF ] | |
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