PDF EN25QH16 Data sheet ( Hoja de datos )

Número de pieza	EN25QH16
Descripción	16 Megabit Serial Flash Memory
Fabricantes	Eon Silicon Solution
Logotipo
Hay una vista previa y un enlace de descarga de EN25QH16 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! EN25QH16 EN25QH16 16 Megabit Serial Flash Memory with 4Kbyte Uniform Sector FEATURES • Single power supply operation - Full voltage range: 2.7-3.6 volt • Serial Interface Architecture - SPI Compatible: Mode 0 and Mode 3 • 16 M-bit Serial Flash - 16 M-bit/2,048 K-byte/8,192 pages - 256 bytes per programmable page • Standard, Dual or Quad SPI - Standard SPI: CLK, CS#, DI, DO, WP#, HOLD# - Dual SPI: CLK, CS#, DQ0, DQ1, WP#, HOLD# - Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3 • High performance - 104MHz clock rate for Standard SPI - 80MHz clock rate for two data bits - 80MHz clock rate for four data bits • Low power consumption - 12 mA typical active current - 1 μA typical power down current • Uniform Sector Architecture: - 512 sectors of 4-Kbyte - 32 blocks of 64-Kbyte - Any sector or block can be erased individually • Software and Hardware Write Protection: - Write Protect all or portion of memory via software - Enable/Disable protection with WP# pin • High performance program/erase speed - Page program time: 1.3ms typical - Sector erase time: 60ms typical - Block erase time 400ms typical - Chip erase time: 12 seconds typical • Lockable 512 byte OTP security sector • Support Serial Flash Discoverable Parameters (SFDP) signature • Read Unique ID Number • Minimum 100K endurance cycle • Package Options - 8 pins SOP 150mil body width - 8 pins SOP 200mil body width - 8 contact VDFN (5x6mm) - 8 pins PDIP - 24 balls TFBGA (6x8mm) - All Pb-free packages are RoHS compliant • Industrial temperature Range GENERAL DESCRIPTION The EN25QH16 is a 16 Megabit (2,048 K-byte) Serial Flash memory, with enhanced write protection mechanisms. The EN25QH16 supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O using SPI pins: Serial Clock, Chip Select, Serial DQ0(DI), DQ1(DO), DQ2(WP#) and DQ3(HOLD#). SPI clock frequencies of up to 80MHz are supported allowing equivalent clock rates of 160MHz (80MHz x 2) for Dual Output and 320MHz (80MHz x 4) for Quad Output when using the Dual/Quad I/O Fast Read instructions. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The EN25QH16 is designed to allow either single Sector/Block at a time or full chip erase operation. The EN25QH16 can be configured to protect part of the memory as the software protected mode. The device can sustain a minimum of 100K program/erase cycles on each sector or block. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 1 ©2004 Eon Silicon Solution, Inc., Rev. F, Issue Date: 2011/06/01 www.eonssi.com 1 page Table 1. Pin Names EN25QH16 Symbol CLK DI (DQ0) DO (DQ1) CS# WP# (DQ2) HOLD# (DQ3) Vcc Vss NC Pin Name Serial Clock Input Serial Data Input (Data Input Output 0) 1 Serial Data Output (Data Input Output 1) 1 Chip Select Write Protect (Data Input Output 2) 2 HOLD# pin (Data Input Output 3) 2 Supply Voltage (2.7-3.6V) Ground No Connect Note: 1. DQ0 and DQ1 are used for Dual and Quad instructions. 2. DQ2 ~ DQ3 are used for Quad instructions. SIGNAL DESCRIPTION Serial Data Input, Output and IOs (DI, DO and DQ0, DQ1, DQ2, DQ3) The EN25QH16 support standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge CLK. Dual and Quad SPI instruction use the bidirectional IO pins to serially write instruction, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Serial Clock (CLK) The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Mode") Chip Select (CS#) The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2 and DQ3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. When CS# is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, CS# must transition from high to low before a new instruction will be accepted. Hold (HOLD#) The HOLD# pin allows the device to be paused while it is actively selected. When HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same SPI signals. The HOLD# function is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial Data IO (DQ3) for Quad I/O operation. Write Protect (WP#) The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (BP0, BP1, BP2 and BP3) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WP# function is only available for standard SPI and Dual SPI operation, when during Quad SPI, this pin is the Serial Data IO (DQ2) for Quad I/O operation. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 5 ©2004 Eon Silicon Solution, Inc., Rev. F, Issue Date: 2011/06/01 www.eonssi.com 5 Page Table 3. Protected Area Sizes Sector Organization EN25QH16 Status Register Content Memory Content BP3 Bit 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BP2 Bit 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BP1 Bit 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BP0 Bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Protect Areas None Block 31 Block 30 to 31 Block 28 to 31 Block 24 to 31 Block 16 to 31 All All None Block 0 Block 0 to 1 Block 0 to 3 Block 0 to 7 Block 0 to 15 All All Addresses None 1F0000h-1FFFFFh 1E0000h-1FFFFFh 1C0000h-1FFFFFh 180000h-1FFFFFh 100000h-1FFFFFh 000000h-1FFFFFh 000000h-1FFFFFh None 000000h-00FFFFh 000000h-01FFFFh 000000h-03FFFFh 000000h-07FFFFh 000000h-0FFFFFh 000000h-1FFFFFh 000000h-1FFFFFh Density(KB) Portion None 64KB 128KB 256KB 512KB 1024KB 2048KB 2048KB None 64KB 128KB 256KB 512KB 1024KB 2048KB 2048KB None Upper 1/32 Upper 2/32 Upper 4/32 Upper 8/32 Upper 16/32 All All None Lower 1/32 Lower 2/32 Lower 4/32 Lower 8/32 Lower 16/32 All All INSTRUCTIONS All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK). The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Dual Output Fast Read (3Bh), Dual I/O Fast Read (BBh), Quad Input/Output FAST_READ (EBh), Read Status Register (RDSR), Read Information Register (RDIFR) or Release from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down (RES ) minimum number of bytes specified has to be given, without which, the command will be ignored. In the case of Page Program, if the number of byte after the command is less than 4 (at least 1 data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must, any less or more will cause the command to be ignored. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. 11 ©2004 Eon Silicon Solution, Inc., Rev. F, Issue Date: 2011/06/01 www.eonssi.com 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet EN25QH16.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
EN25QH16	16 Megabit Serial Flash Memory	Eon Silicon Solution

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar