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PDF LTC2351-12 Data sheet ( Hoja de datos )
| Número de pieza | LTC2351-12 | |
| Descripción | 1.5Msps Simultaneous Sampling ADC | |
| Fabricantes | Linear | |
| Logotipo |  |
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LTC2351-12
FEATURES
6 Channel, 12-Bit, 1.5Msps
Simultaneous Sampling ADC
With Shutdown
DESCRIPTION
n 1.5Msps ADC with 6 Simultaneously Sampled
Differential Inputs
n 250ksps Throughput per Channel
n 72dB SINAD
n Low Power Dissipation: 16.5mW
n 3V Single Supply Operation
n 2.5V Internal Bandgap Reference, Can be Overdriven
With External Reference
n 3-Wire SPI-Compatible Serial Interface
n Internal Conversion Triggered by CONV
n SLEEP (12μW) Shutdown Mode
n NAP (4.5mW) Shutdown Mode
n 0V to 2.5V Unipolar, or ±1.25V Bipolar Differential
Input Range
n 83dB Common Mode Rejection
n Tiny 32-Pin (5mm × 5mm) QFN Package
APPLICATIONS
n Multiphase Power Measurement
n Multiphase Motor Control
n Data Acquisition Systems
n Uninterruptable Power Supplies
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6084440, 6522187.
The LTC®2351-12 is a 12-bit, 1.5Msps ADC with six simul-
taneously sampled differential inputs. The device draws
only 5.5mA from a single 3V supply, and comes in a tiny
32-pin (5mm × 5mm) QFN package. A Sleep shutdown
mode further reduces power consumption to 12μW. The
combination of low power and tiny package makes the
LTC2351-12 suitable for portable applications.
The LTC2351-12 contains six separate differential inputs
that are sampled simultaneously on the rising edge of the
CONV signal. These six sampled inputs are then converted
at a rate of 250ksps per channel.
The 83dB common mode rejection allows users to eliminate
ground loops and common mode noise by measuring
signals differentially from the source.
The device converts 0V to 2.5V unipolar inputs differentially,
or ±1.25V bipolar inputs also differentially, depending on the
state of the BIP pin. Any analog input may swing rail-to-rail
as long as the differential input range is maintained.
The conversion sequence can be abbreviated to convert
fewer than six channels, depending on the logic state of
the SEL2, SEL1 and SEL0 inputs.
The serial interface sends out the six conversion results in 96
clocks for compatibility with standard serial interfaces.
BLOCK DIAGRAM
CH5– CH5+
21 20 19
CH4– CH4+
18 17 16
CH3–
15
CH3+
14 12
13
CH2– CH2+
11 10 9
CH1– CH1+
8 76
CH0– CH0+
54
–
S AND H
–
S AND H
–
S AND H
–
S AND H
–
S AND H
–
S AND H
MUX
2.5V
REFERENCE
10μF 3V
VCC VDD
24 25
1.5Msps
12-BIT ADC
12-BIT LATCH 0
12-BIT LATCH 1
12-BIT LATCH 2
12-BIT LATCH 3
12-BIT LATCH 4
12-BIT LATCH 5
TIMING
LOGIC
33 22
23 29
GND 10μF VREF BIP
26 27 28
SEL2 SEL1 SEL0
THREE-
STATE
SERIAL
OUTPUT
PORT
OVDD
3V
3
SD0
1
OGND
2
CONV
30
SCK
32
DGND
31
235112 TA01
0.1μF
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1 page  
LTC2351-12
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V.
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX
UNITS
t9 SCK↑ to Hi-Z at SDO
(Notes 6, 12)
6 ns
t10 Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
2
ns
t11 VREF Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
2 ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above VDD, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than VDD without latchup.
Note 4: Offset and range specifications apply for a single-ended CH0+
– CH5+ input with CH0– – CH5– grounded and using the internal 2.5V
reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band. Linearity is tested for CH0 only.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between CHx+ and CHx–, x = 0 to 5.
Note 9: The absolute voltage at CHx+ and CHx– must be within this range.
Note 10: If less than 3ns is allowed, the output data will appear one
clock cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
96th rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10μF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5VP-P input sine wave.
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The conversion process takes 16 clocks for each channel that is
enabled, up to 96 clocks for all 6 channels.
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TIMING DIAGRAMS
LTC2351-12
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11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC2351-12.PDF ] | |
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