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PDF LTC2226H Data sheet ( Hoja de datos )
| Número de pieza | LTC2226H | |
| Descripción | ADC | |
| Fabricantes | Linear | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2226H (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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FEATURES
n Sample Rate: 25Msps
n –40°C to 125°C Operation
n Single 3V Supply (2.8V to 3.5V)
n Low Power: 75mW
n 71.4dB SNR
n 90dB SFDR
n No Missing Codes
n Flexible Input: 1VP-P to 2VP-P Range
n 575MHz Full Power Bandwidth S/H
n Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Pin Compatible Family
n LTC2246H (14-Bit), LTC2226H (12-Bit)
n 48-Pin (7mm × 7mm) LQFP Package
APPLICATIONS
n Automotive
n Industrial
n Wireless and Wired Broadband Communication
TYPICAL APPLICATION
REFH
REFL
ANALOG
INPUT
FLEXIBLE
REFERENCE
+
INPUT
– S/H
CLOCK/DUTY
CYCLE
CONTROL
CLK
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
LTC2226H
12-Bit, 25Msps
125°C ADC in LQFP
DESCRIPTION
The LTC®2226H is a 12-bit 25Msps, low power 3V A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2226H is perfect for
demanding imaging and communications applications
with AC performance that includes 71.4dB SNR and 90dB
SFDR.
DC specs include ±0.3LSB INL (typ), ±0.3LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.25LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high performance
at full speed for a wide range of clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
OUTPUT
DRIVERS
OVDD
D11
•
•
•
D0
OGND
2226 TA01
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
0
Typical INL, 2V Range
1024
2048
CODE
3072
4096
2226 TA01b
2226hfc
1
1 page  
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 25MHz, input range = 2VP-P with differential
drive, unless otherwise noted.
LTC2226H
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 25MHz, input range = 1VP-P with
differential drive.
Note 9: Recommended operating conditions.
TYPICAL PERFORMANCE CHARACTERISTICS
Typical INL, 2V Range, 25Msps
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
0
1024
2048
CODE
3072
4096
2226H G01
–811d9B2,P2oVinRt aFnFgT,ef,IN25=M3s0pMsHz,
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 2 4 6 8 10 12
FREQUENCY (MHz)
2226H G04
Typical DNL, 2V Range, 25Msps
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
0
1024
2048
CODE
3072
4096
2226H G02
8–119d2B,P2oVinRt aFnFgT,ef,IN25=M7s0pMsHz,
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 2 4 6 8 10 12
FREQUENCY (MHz)
2226H G05
8192 Point FFT, fIN = 5MHz, –1dB,
2V Range, 25Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 2 4 6 8 10 12
FREQUENCY (MHz)
2226H G03
–811d9B2,P2oVinRt aFnFgT,ef,IN25=M1s4p0sMHz,
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 2 4 6 8 10 12
FREQUENCY (MHz)
2226H G06
2226hfc
5
5 Page 
LTC2226H
APPLICATIONS INFORMATION
Input Drive Impedance
As with all high performance, high speed ADCs, the dy-
namic performance of the LTC2226H can be influenced by
the input drive circuitry, particularly the second and third
harmonics. Source impedance and reactance can influence
SFDR. At the falling edge of CLK, the sample-and-hold
circuit will connect the 4pF sampling capacitor to the input
pin and start the sampling period. The sampling period
ends when CLK rises, holding the sampled input on the
sampling capacitor. Ideally the input circuitry should be
fast enough to fully charge the sampling capacitor during
the sampling period 1/(2FENCODE); however, this is not
always possible and the incomplete settling may degrade
the SFDR. The sampling glitch has been designed to be
as linear as possible to minimize the effects of incomplete
settling.
For the best performance, it is recommended to have a
source impedance of 100W or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2226H being driven by an RF
transformer with a center tapped secondary. The secondary
center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
VCM
ANALOG
INPUT
0.1µF
T1
1:1
25Ω
25Ω 0.1µF
25Ω 25Ω
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2.2µF
AIN+
LTC2226H
12pF
AIN–
2226H F03
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen
by the ADC does not exceed 100W for each ADC input.
A disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of most op amps will limit the SFDR at high
input frequencies.
Figure 5 shows a single-ended input circuit. The impedance
seen by the analog inputs should be matched. This circuit
is not recommended if low distortion is required.
The 25Ω resistors and 12pF capacitor on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input.
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER 25Ω
++
CM
––
25Ω
VCM
2.2µF
AIN+
LTC2226H
12pF
AIN–
2226H F04
Figure 4. Differential Drive with an Amplifier
ANALOG
INPUT
0.1µF
1k 1k
25Ω
VCM
2.2µF
AIN+
LTC2226H
25Ω
0.1µF
12pF
AIN–
2226H F05
Figure 5. Single-Ended Drive
2226hfc
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet LTC2226H.PDF ] | |
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