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PDF STL3N10F7 Data sheet ( Hoja de datos )
| Número de pieza | STL3N10F7 | |
| Descripción | N-CHANNEL POWER MOSFET | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STL3N10F7
N-channel 100 V, 0.062 Ω typ., 4 A STripFET™ VII DeepGATE™
Power MOSFET in a PowerFLAT™ 2x2 package
Datasheet - production data
Features
1
2
3
1
2
3
6
5
4
PowerFLAT™ 2x2
Order code
STL3N10F7
VDS
100 V
RDS(on) max
0.07 Ω
• N-channel enhancement mode
• Low gate charge
• 100% avalanche rated
ID
4A
Applications
• Switching applications
Figure 1. Internal schematic diagram
1(D) 2(D) 3(G)
DS
Description
th
This device utilizes the 7 generation of design
rules of ST’s proprietary STripFET™ technology,
with a new gate structure. The resulting Power
MOSFET exhibits the lowest RDS(on) in all
packages.
6(D) 5(D) 4(S)
Bottom view
AM11269v1
Order code
STL3N10F7
Table 1. Device summary
Marking
Packages
ST3N
PowerFLAT™ 2x2
Packaging
Tape and reel
April 2014
This is information on a product in full production.
DocID025948 Rev 2
1/13
www.st.com
1 page  
STL3N10F7
Electrical characteristics
Symbol
Table 7. Source drain diode
Parameter
Test conditions
Min. Typ. Max. Unit
ISD
(1)
ISDM
(2)
VSD
trr
Qrr
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
IRRM Reverse recovery current
ISD= 2 A, VGS=0
ISD= 2 A,
di/dt = 100 A/μs,
VDD= 80 V, Tj=150 °C
(see Figure 18)
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 μs, duty cycle 1.5 %
- 4A
- 16 A
- 1.1 V
- 30
ns
- 24
nC
- 1.6
A
DocID025948 Rev 2
5/13
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5 Page 
STL3N10F7
Package mechanical data
Dim.
A
A1
A3
b
D
E
D2
E2
e
K
K1
K2
L
L1
Table 8. PowerFLAT™ 2 x 2 mechanical data
mm.
Min.
Typ.
0.70 0.75
0.00 0.02
0.20
0.25 0.30
1.90 2.00
1.90 2.00
0.90 1.00
0.80 0.90
0.55 0.65
0.15 0.25
0.20 0.30
0.25 0.35
0.20 0.25
0.65 0.75
Max.
0.80
0.05
0.35
2.10
2.10
1.10
1.00
0.75
0.35
0.40
0.45
0.30
0.85
Figure 20. PowerFLAT™ 2x2 recommended footprint (all dimensions are in mm)
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Footprint
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