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PDF STHVDAC-253MTG Data sheet ( Hoja de datos )
| Número de pieza | STHVDAC-253MTG | |
| Descripción | Antenna tuning circuit | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STHVDAC-253MTG
Antenna tuning circuit with turbo and glide
/HDGIUHH)OLS&KLS
EXPSV
Features
Dedicated controller to bias BST tunable
capacitors
Operation compliant with cellular systems
requirements
Turbo and glide modes for optimal system
performance
Integrated boost converter with 3
programmable outputs (from 0 to 24 V)
Low power consumption
MIPI RFFE serial interface 1,8 V
Available in WLCSP for stand-alone or SiP
module integration
Applications
Cellular antenna tunable matching network in
multi-band GSM/WCDMA/LTE handsets
Compatible for open loop antenna tuner
application
Benefits
RF tunable passive implementation in mobile
phones to optimize the radiated performance.
Datasheet - production data
Description
The ST high voltage BST capacitor controller
STHVDAC-253MTG is a high voltage digital to
analog converter (DAC), specifically designed to
control and meet the wide tuning bias voltage
requirement of the BST tunable capacitors.
It provides 3 independent high voltage outputs,
thus having the capability to control 3 different
capacitors. It is fully controlled through an RFFE
serial interface.
BST capacitors are tunable capacitors intended
for use in mobile phone application, and
dedicated to RF tunable application. These
tunable capacitors are controlled through a bias
voltage ranging from 0 to 24 V. The
implementation of BST tunable capacitor in
mobile phones enables significant improvement
in term of radiated performance, making the
performance almost insensitive to external
environment.
Figure 1. Pin configuration (top view)
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November 2015
This is information on a product in full production.
DocID027917 Rev 4
1/28
www.st.com
1 page  
STHVDAC-253MTG
2 Functional block diagram
Functional block diagram
Figure 2. HVDAC functional block diagram
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DocID027917 Rev 4
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28
5 Page 
STHVDAC-253MTG
Devices operating modes
Figure 5. HVDAC state diagram
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4.4 Device reset
Power-On Reset is implemented on the VI/O supply input, ensuring the HVDAC will be reset
to default mode once VI/O supply line rises above a given threshold (typically 1V). This
trigger will force all registers to their default value.
Device Reset is also implemented as defined in the MIPI RFFE specification. Setting
PWR_MODE bits to 01b will force the device to reset all registers to their default value, and
then automatically switch the device into low power mode.
A Soft Reset is implemented using register #26 MSB. Setting this bit will reset all registers to
their default values, except PM_TRIG register (reg #28) and device USID (reg #31).
4.5 RFFE serial interface
The HVDAC is fully controlled through RFFE serial interface (DATA, VIO, CLOCK).
This interface is further described in the next sections of this document and is made
compliant to the MIPI Alliance Specification for RF Front End control Interface version 1.10 -
26 July 2011 (see Figure 12 and Figure 13).
Sequence Start Condition (SSC): One rising edge followed by falling edge on DATA while
CLK remains at logic level low. This is used by the Master to identify the start of a Command
frame.
Parity (P): Each frame shall end with a single parity bit. The parity bit shall be driven such
that the total number of bits in the frame that are driven to logic level one, including the
parity bit, is odd.
DocID027917 Rev 4
11/28
28
11 Page | ||
| Páginas | Total 28 Páginas | |
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