PDF LTC4266 Data sheet ( Hoja de datos )

Número de pieza	LTC4266
Descripción	Quad IEEE 802.3at Power over Ethernet Controller
Fabricantes	Linear Technology
Logotipo
Hay una vista previa y un enlace de descarga de LTC4266 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! FEATURES nn Four Independent PSE Channels nn Compliant with IEEE 802.3at Type 1 and 2 nn 0.34Ω Total Channel Resistance nn 130mW/Port at 600mA nn Advanced Power Management nn 8-Bit Programmable Current Limit (ILIM) nn 7-Bit Programmable Overload Currents (ICUT) nn Fast Shutdown of Preselected Ports nn 14.5-Bit Port Current/Voltage Monitoring nn 2-Event Classification nn Very High Reliability 4-Point PD Detection nn 2-Point Forced Voltage nn 2-Point Forced Current nn High Capacitance Legacy Device Detection nn LTC4259A-1 and LTC4258 Pin and SW Compatible nn 1MHz I2C Compatible Serial Control Interface nn Midspan Backoff Timer nn Supports Proprietary Power Levels Above 25W nn Available in 38-Pin 5mm × 7mm QFN and 36-Pin SSOP Packages APPLICATIONS nn High Power PSE Switches/Routers nn High Power PSE Midspans L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. LTC4266 Quad IEEE 802.3at Power over Ethernet Controller DESCRIPTION The LTC®4266 is a quad PSE controller designed for use in IEEE 802.3 Type 1 and Type 2 (high power) compliant Power over Ethernet systems. External power MOSFETs enhance system reliability and minimize channel resistance, cutting power dissipation and eliminating the need for heatsinks even at Type 2 power levels. External power components also allow use at very high power levels while remaining otherwise compatible with the IEEE standard. 80V-rated port pins provide robust protection against external faults. The LTC4266 includes advanced power management features, including current and voltage readback and pro- grammable ICUT and ILIM thresholds. Available C libraries simplify power-management software development; an optional AUTO pin mode provides fully IEEE-compliant standalone operation with no software required. Proprietary 4-point PD detection circuitry minimizes false PD detec- tion while supporting legacy phone operation. Midspan operation is supported with built-in 2-event classification and backoff timing. Host communication is via a 1MHz I2C serial interface. The LTC4266 is available in a 5mm × 7mm QFN package that significantly reduces board space compared with competing solutions. A legacy-compatible 36-pin SSOP package is also available. TYPICAL APPLICATION Complete 4-Port Ethernet High Power Source 3.3V 10Ω + SMAJ5.0A 10µF 10Ω + CBULK –54V SMAJ58A TVSBULK VDD 0.1µF AD0 AD1 AD2 AD3 DGND SHDN1 SHDN2 SHDN3 SHDN4 LTC4266 AUTO MSD RESET MID SDAIN SCL SDAOUT INT AGND 1µF 100V VEE SENSE1 GATE1 OUT1 SENSE2 GATE2 OUT2 SENSE3 GATE3 OUT3 SENSE4 GATE4 OUT4 0.22µF 100V ×4 S1B ×4 S1B ×4 –54V PORT1 PORT2 PORT3 PORT4 4266 TA01 For more information www.linear.com/LTC4266 4266ff 1 1 page LTC4266 E LECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise otherwise noted. (Notes 3, 4) specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless SYMBOL PARAMETER Timing Characteristics CONDITIONS MIN TYP MAX UNITS tDET tDETDLY tCLE1 tME1 tCLE2 tME2 tCLE3 tPON Detection Time Detection Delay First Class Event Duration First Mark Event Duration Second Class Event Duration Second Mark Event Duration Third Class Event Duration Power On Delay in AUTO pin mode Turn On Rise Time Turn On Ramp Rate Fault Delay Midspan Mode Detection Backoff Beginning to End of Detection (Note 7) l 270 290 310 From PD Connected to Port to Detection Complete (Note 7) l 300 470 (Note 7) l 11 12 13 (Notes 7, 11) l 6.8 8.6 10.3 (Note 7) l 11 12 13 (Note 7) l 19 22 CPORT = 0.6µF (Note 7) From End of Valid Detect to Application of Power to Port (Note 7) l l 0.1 60 (AGND – VOUT): 10% to 90% of (AGND – VEE), CPORT = 0.15µF (Note 7) l 15 24 CPORT = 0.15µF (Note 7) l 10 From ICUT Fault to Next Detect l 1.0 1.1 Rport = 15.5kΩ (Note 7) l 2.3 2.5 2.7 ms ms ms ms ms ms ms ms µs V/µs s s tSTART tLIM tCUT Power Removal Detection Delay From Power Removal After tDIS to Next l 1.0 1.3 2.5 Detect (Note 7) Maximum Current Limit Duration During Port tSTART1 = 0, tSTART0 = 0 (Notes 7, 12) Start-Up l 52 62.5 66 Maximum Current Limit Duration After Port tCUT1 = 0, tCUT0 = 0, tLIM = 0h (Notes 7, 12) l 52 62.5 66 Start-Up Maximum Overcurrent Duration After Port Start-Up tCUT1 = 0, tCUT0 = 0 (Notes 7, 12) l 52 62.5 66 Maximum Overcurrent Duty Cycle (Note 7) l 5.8 6.3 6.7 s ms ms ms % tMPS tDIS tMSD tSHDN Maintain Power Signature (MPS) Pulse Width Current Pulse Width to Reset Disconnect Sensitivity Timer (Notes 7, 8) l 1.6 3.6 Maintain Power Signature (MPS) Dropout Time tconf [1:0] = 00b (Notes 5, 7, 12) l 320 350 380 Masked Shut Down Delay (Note 7) l 6.5 Port Shut Down Delay (Note 7) l 6.5 I2C Watchdog Timer Duration l 1.5 2 3 ms ms µs µs s Minimum Pulse Width for Masked Shut Down Minimum Pulse Width for SHDN (Note 7) (Note 7) l3 l3 µs µs Minimum Pulse Width for RESET (Note 7) l 4.5 µs For more information www.linear.com/LTC4266 4266ff 5 5 Page I2C TIMING DIAGRAMS LTC4266 SCL SDA 0 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK START BY MASTER ACK BY SLAVE ACK BY SLAVE ACK BY SLAVE STOP BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 REGISTER ADDRESS BYTE FRAME 3 DATA BYTE 4266 F06 Figure 6. Writing to a Register SCL SDA 0 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 0 1 0 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK BY SLAVE ACK BY SLAVE FRAME 2 REGISTER ADDRESS BYTE REPEATED START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK BY SLAVE NO ACK BY MASTER FRAME 2 DATA BYTE STOP BY MASTER 4266 F07 Figure 7. Reading from a Register SCL SDA 0 1 0 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE ACK BY SLAVE FRAME 2 DATA BYTE NO ACK BY MASTER STOP BY MASTER 4266 F08 Figure 8. Reading the Interrupt Register (Short Form) SCL SDA 0 0 0 1 1 0 0 R/W ACK 0 1 0 AD3 AD2 AD1 AD0 1 ACK START BY MASTER FRAME 1 ALERT RESPONSE ADDRESS BYTE ACK BY NO ACK BY SLAVE MASTER FRAME 2 SERIAL BUS ADDRESS BYTE STOP BY MASTER 4266 F09 Figure 9. Reading from Alert Response Address For more information www.linear.com/LTC4266 4266ff 11 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet LTC4266.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
LTC4260	Positive High Voltage Hot Swap Controller	Linear Technology
LTC4261	Negative Voltage Hot Swap Controllers	Linear Technology
LTC4261-2	Negative Voltage Hot Swap Controllers	Linear Technology
LTC4263	Single IEEE 802.3af Compliant PSE Controller	Linear Technology

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar