|
|
PDF LTC4260 Data sheet ( Hoja de datos )
| Número de pieza | LTC4260 | |
| Descripción | Positive High Voltage Hot Swap Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LTC4260 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Features
n Allows Safe Board Insertion into Live Backplane
n 8-Bit ADC Monitors Current and Voltage
n I2C™/SMBus Interface
n Wide Operating Voltage Range: 8.5V to 80V
n High Side Drive for External N-Channel MOSFET
n Input Overvoltage/Undervoltage Protection
n Optional Latchoff or Autoretry After Faults
n Alerts Host After Faults
n Foldback Current Limiting
n Available in 24-Lead SO, 24-Lead Narrow
SSOP and 32-Lead (5mm × 5mm) QFN Packages
Applications
n Electronic Circuit Breakers
n Live Board Insertion
n Computers, Servers
LTC4260
Positive High Voltage
Hot Swap Controller with
I2C Compatible Monitoring
Description
The LTC®4260 Hot Swap™ controller allows a board to be
safely inserted and removed from a live backplane. Using
an external N-channel pass transistor, the board supply
voltage can be ramped up at an adjustable rate. An I2C
interface and onboard ADC allow monitoring of board
current, voltage and fault status.
The device features adjustable analog foldback current
limit with latch off or automatic restart after the LTC4260
remains in current limit beyond an adjustable time-out
delay.
The controller has additional features to interrupt the host
when a fault has occurred, notify when output power is
good, detect insertion of a load card and power-up in
either the on or off state.
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
Typical Application
48V
SDA
SCL
ALERT
GND
BACKPLANE PLUG-IN
CARD
*DIODES INC. SMBT70A
3A, 48V Card Resident Application
49.9k
0.1µF
1.74k
0.010Ω FDB3632
10Ω 100k
6.8nF
+
CL
*
2.67k
UV VDD
OV
SENSE GATE
SOURCE
FB
SDAO
SDAI
SCL
ALERT
LTC4260
BD_PRST
ADIN
ON INTVCC
TIMER
GND GPIO
0.1µF
68nF
4260 TA01
VOUT
48V
43.5k
3.57k
24k
Power Up Waveforms
VIN
50V/DIV
IIN
2A/DIV
CL = 1000F
VOUT
50V/DIV
GPIO
5V/DIV
25ms/DIV
4260 TA02
For more information www.linear.com/LTC4260
4260fc
1
1 page  
LTC4260
E lectrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 48V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
I2C Interface Timing (Note 4)
fSCL(MAX)
Maximum SCL Clock Frequency
Operates with fSCL ≤ fSCL(MAX)
400
kHz
tBUF(MIN)
Minimum Bus Free Time Between
Stop/Start Condition
0.12 1.3
µs
tSU,STA(MIN)
Minimum Repeated Start Condition
Set-Up Time
30 600
ns
tHD,STA(MIN)
Minimum Hold Time After (Repeated)
Start Condition
140 600
ns
tSU,STO(MIN)
Minimum Stop Condition Set-Up Time
30 600
ns
tSU,DAT(MIN)
tHD,DATI(MIN)
tHD,DATO(MIN)
tSP(MAX)
CX
Minimum Data Set-Up Time Input
Minimum Data Hold Time Input
Minimum Data Hold Time Output
Maximum Suppressed Spike Pulse Width
SCL, SDA Input Capacitance
SDAI Tied to SDAO
30 100
–100 0
300 500 900
50 110 250
5 10
ns
ns
ns
ns
pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specified.
Note 3: Limits on maximum rating is defined as whichever limit occurs first.
An internal clamp limits the GATE pin to a minimum of 10V above source.
Driving this pin to voltages beyond the clamp may damage the device.
Note 4: Guaranteed by design and not subject to test.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
precise analog input voltage. Maximum specifications are limited by the
LSB step size and the single shot measurement. Typical specifications are
measured from the 1/4, 1/2 and 3/4 areas of the quantization band.
Note 6: For the VDD-SENSE channel, full-scale is at code 255 but codes
above 200 may be discarded by offset cancellation. Full scale error and
total unadjusted error are evaluated over the 0-200 code range. Full scale
voltage corresponds to the theoretical code 255, and is extrapolated from
a code 200 measurement.
For more information www.linear.com/LTC4260
4260fc
5
5 Page 
timing Diagram
SDAI/SDAO
SCL
tHD, STA
START
CONDITION
tSU, DAT
tHD, DATO,
tHD, DATI
LTC4260
tSU, STA
tSP
tHD, STA
tSP
tSU, STO
tBUF
4260 TD01
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
Operation
The Functional Diagram displays the main functional areas
of this device. The LTC4260 is designed to turn a board’s
supply voltage on and off in a controlled manner, allowing
the board to be safely inserted or removed from a live
backplane. During normal operation, the charge pump
and gate driver turn on the external N-channel pass FET’s
gate to pass power to the load. The gate driver uses a
charge pump that derives its power from the SOURCE pin.
When the SOURCE pin is at ground, the charge pump is
powered from an internal 12V supply derived from VDD.
This results in a 200µA current load on the SOURCE pin
when the gate is up. Also included in the gate driver is an
internal 15V gate-to-source clamp.
The current sense (CS) amplifier monitors the load cur-
rent using the difference between the VDD and SENSE pin
voltage. The CS amplifier limits the current in the load by
reducing the GATE-to-SOURCE voltage in an active control
loop. The CS amplifier requires 100µA input bias current
from both the VDD and the SENSE pins.
A short circuit on the output to ground causes significant
power dissipation during active current limiting. To limit
this power, the foldback amplifier reduces the current limit
value from 50mV to 20mV (referred to the VDD minus
SENSE voltage) in a linear manner as the FB pin drops
below 2V (see Typical Performance curves).
If an overcurrent condition persists, the TIMER pin ramps
up with a 100µA current source until the pin voltage
exceeds 1.2V (comparator TM2). This indicates to the
logic that it is time to turn off the pass FET to prevent
overheating. At this point the TIMER pin ramps down us-
ing the 2µA current source until the voltage drops below
0.2V (comparator TM1) which tells the logic that the pass
transistor has cooled and it is safe to turn it on again.
The output voltage is monitored using the FB pin and the
PG comparator to determine if the power is available for
the load. The power good condition is signalled by the
GPIO pin using an open-drain pull-down transistor. The
GPIO pin can also be used as a general purpose input (GP
comparator) or output pin.
The Functional Diagram shows the monitoring blocks of
the LTC4260. The group of comparators on the left side
includes the UV, OV, RST, BP and ON comparators. These
comparators are used to determine if the external condi-
tions are valid prior to turning on the FET. But first the
two undervoltage lockout circuits UVLO1 and UVLO2 must
validate the input supply and the internally generated 5.5V
supply (INTVCC) and generate the power up initialization
to the logic circuits.
Included in the LTC4260 is an 8-bit A/D converter. The
converter has a 3-input mux to select between the ADIN
pin, the SOURCE pin and the VDD – SENSE voltage.
An I2C interface is provided to read the A/D registers. It also
allows the host to poll the device and determine if faults
have occurred. If the ALERT line is used as an interrupt,
the host can respond to a fault in real time. The typical SDA
line is divided into an SDAI (input) and SDAO (output).
This simplifies applications using an optoisolator driven
directly from the SDAO output. The I2C device address is
decoded using the ADR0, ADR1 and ADR2 pins. These
inputs have three states each that decode into a total of
27 device addresses.
For more information www.linear.com/LTC4260
4260fc
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC4260.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LTC4260 | Positive High Voltage Hot Swap Controller | Linear Technology |
| LTC4261 | Negative Voltage Hot Swap Controllers | Linear Technology |
| LTC4261-2 | Negative Voltage Hot Swap Controllers | Linear Technology |
| LTC4263 | Single IEEE 802.3af Compliant PSE Controller | Linear Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |