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PDF LT8709 Data sheet ( Hoja de datos )
| Número de pieza | LT8709 | |
| Descripción | Negative Input Synchronous Multi-Topology DC/DC Controller | |
| Fabricantes | Linear | |
| Logotipo |  |
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LT8709
Features
Negative Input
Synchronous Multi-Topology
DC/DC Controller
Description
n Wide Negative Input Range: –4.5V to –80V
n Rail-to-Rail Output Current Monitor and Control
n Input Voltage Regulation for High Impedance Inputs
n Power Good Indication Pin
n MODE Pin for Forced CCM (Continuous Conduction
Mode) or Pulse-Skipping/DCM (Discontinuous
Conduction Mode) Operation
n Switching Frequency Up to 750kHz
n Easily Configurable as a Buck, Boost, Buck-Boost, or
Inverting Converter with a Single Feedback Pin
n Can be Synchronized to an External Clock
n High Gain EN/FBIN Pin Accepts Slowly Varying Input
Signals
n 20-Lead TSSOP Package
Applications
n High Power Negative Input, Negative Output Power
Supplies
n High Power Negative Input, Positive Output Power
Supplies
n Telecom Equipment Power Supplies
n Cathodic Protection Power Supplies
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
The LT®8709 is a synchronous PWM controller for negative-
to-negative or negative-to-positive DC/DC conversion,
with rail-to-rail output current monitor and control. The
LT8709 is ideal for many local power supply designs. It
can be easily configured in buck, boost, buck-boost, and
inverting topologies with negative input voltages.
In addition, the LT8709’s rail-to-rail output current sense
allows the part to be configured in current limited applica-
tions such as battery or capacitor charging. The PG pin
is used for power good indication.
The LT8709’s switching frequency range can be set between
100kHz and 750kHz. The part may be clocked internally
at a frequency set by the resistor from the RT pin to the
–VIN pin, or it may be synchronized to an external clock.
The LT8709 also features innovative EN/FBIN pin circuitry
that allows for slowly varying input signals and an adjust-
able undervoltage lockout function. The pin is also used as
input voltage regulation to avoid collapsing a high imped-
ance input supply. Additional features such as frequency
foldback, thermal shutdown and soft-start are integrated.
The LT8709 is available in a 20-lead TSSOP package.
Typical Application
250kHz, –16V to –30V Input to –12V/8.5A Output Buck
7.3µH
4mΩ
10µF
×6
2.2µF
+ 120µF
62.5k
10k 2.2µF
100k
–VIN
–16V TO –30V
143k
2mΩ
–VIN
TG CSP CSN
GND
EN/FBIN LT8709
BG
ISN
ISP
FBY
INTVCC
MODE
PG
RT
SYNC
–VIN
IMON
68nF
BIAS
INTVEE
VC
SS
470nF
2.2µF
100pF
5.9k
2.2nF
VOUT
–12V
8.5A
150µF
22µF
×3
33k
4.99k
2.2µF
8709 TA01a
For more information www.linear.com/LT8709
Efficiency and Power Loss
vs Load Current (–VIN = –24V)
100 4.5
90 4.0
80 3.5
70 3.0
60 2.5
50 2.0
40 1.5
30 1.0
20 0.5
10 0
01 23456789
LOAD CURRENT (A)
8709 TA01b
8709f
1
1 page  
LT8709
E lectrical Characteristics The l denotes the specifications which apply over the full operating
temperature range,
VBIAS – V–VIN = 12V,
otherwise specifications
unless otherwise noted.
fPoirnevaoclhtacgheasnhnaevleartheeaftoTllAo=wi2n5g°Cre.lVaGtiNoDns–:
VF–BVYINis=r1e2laVt,ivVeENto/FtBhINe
–GNV–DVIpNin=,1T2GVa, nd
INTVEE
to the BIAS
denoted as
cpuinrr,eanntdflaolwl iontgheirntpointhsetopitnh;en–eVgINatpivien,cuunrrleesnst
otherwise
is denoted
stated. Pin
as current
currents have
flowing out of
the
the
following relations: positive current is
pin, unless otherwise stated. (Note 2)
PARAMETER
Oscillator
Switching Frequency, fOSC
Switching Frequency in Foldback
Switching Frequency Range
SYNC High Level for Sync
SYNC Low Level for Sync
SYNC Clock Pulse Duty Cycle
Recommended Min SYNC Ratio
Gate Drivers, BG and TG
BG Rise Time
BG Fall Time
TG Rise Time
TG Fall Time
BG and TG Non-Overlap Time
BG Minimum On-Time
BG Minimum Off-Time
TG Minimum On-Time
TG Minimum Off-Time
Power Good Indicators, PG
PG Power Good Threshold for Negative
FBY Voltage
PG Power Good Threshold for Positive
FBY Voltage
PG Power Good Hysteresis for Negative
FBY Voltage
PG Power Good Hysteresis for Positive
FBY Voltage
CONDITIONS
RT = 46.4k
RT = 357k
Compared to Normal fOSC
Free-Running or Synchronizing
VSYNC = 0V to 3V
fSYNC/fOSC
CBG = 3300pF (Note 3)
CBG = 3300pF (Note 3)
CTG = 3300pF (Note 3)
CTG = 3300pF (Note 3)
TG Rising to BG Rising, CBG = CTG = 3300pF (Note 3)
BG Falling to TG Falling, CBG = CTG = 3300pF (Note 3)
CBG = CTG = 3300pF
CBG = CTG = 3300pF
CBG = CTG = 3300pF
CBG = CTG = 3300pF
Current Out of FBY Pin Rising
Current Out of FBY Pin Falling
Current into FBY Pin Rising
Current into FBY Pin Falling
MIN TYP MAX UNITS
l 640 750 860
l 85 100 115
1/5
l 100
750
l 1.5
l 0.4
20 80
3/4
kHz
kHz
ratio
kHz
V
V
%
24
21
15
16
80 140 220
45 90 150
150 420
100 480
0 150
290 770
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
l 71 74.9 79
l 63.5 67.5 71.5
l 71.5 75.4 79.5
l 63.5 67.5 71.5
7.4
7.9
µA
µA
µA
µA
µA
µA
PG Anti-Glitch Delay
PG Output Voltage Low
PG Leakage Current
Delay from PG Threshold Trip to PG Toggle
100µA into PG Pin, |IFBY| < PG Threshold
VPG = 7V, |IFBY| > PG Threshold
100 µs
l
9 50
mV
0.01 1
µA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT8709E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the
–40°C to 125°C operating temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT8709I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation over the specified maximum operating junction
temperature may impair device reliability.
Note 5: Do not apply a positive or negative voltage or current source to the
BG, TG, and INTVEE pins, otherwise permanent damage may occur, except
INTVEE may be connected to –VIN if BIAS is connected to INTVCC.
For more information www.linear.com/LT8709
8709f
5
5 Page 
Block Diagram
LT8709
CIN
–VIN
MP L1
MN
TG
RSENSE1
–VIN
TG
RSENSE2
VOUT
COUT
GND
CSP CSN
BG INTVCC
BIAS TG BIAS
BIAS
LDO LOGIC
DRIVER
LEVEL
SHIFT
DRIVER
LDO
6.3V
CVCC
–VIN
RIN1
RIN2
–VIN
CSS
–VIN
INTVCC
LDO
UVLO
1.213V
REFERENCE
EN/FBIN
EN/FBIN
LOGIC
51.4k
1.3V
MODE
–VIN
+
1.7V
1.224V
1.8V
SS
–
+ DCM_EN
–
2.7V 50mV
260k
+
–
START-UP
AND RESET
LOGIC
+
–
+
–
DRIVER
–VIN DISABLE
–VIN FBX
FREQUENCY
DCM_EN
FOLDBACK
–
+A5
IMON
1.38V
DIE TEMP
175°C
–VIN
SR1
Q
S
R
TG DRIVER
DISABLE
DCM_EN ISP ISN
1.155V
FBX
UVLO
+
–
A6 1:1
Q1
BIAS – 6.18V
PG 100µs
ANTI-GLITCH
–+ 1.234V
INTVEE
PG
–VIN
FBY
–
M1
+
SLOPE
COMPENSATION
÷N ADJUSTABLE
OSCILLATOR
SYNC
BLOCK
SS SOFT-START
EN/FBIN
1.607V
+
–EA3
SYNC RT
FBX
1.213V
+
EA1
–
14.5k
14.5k
–VIN
1.213V
EA2
ISN
A7 + – ISP
11.9k
51.8mV
VC IMON–VIN
LOGIC-LO ≤ –VIN + 0.4V
LOGIC-HI ≥ –VIN + 1.5V
NOTE: ALL THE VOLTAGES INSIDE THE CHIP ARE REFERRED TO THE –VIN PIN.
RT
–VIN
RC
CC
–VIN
CF
–VIN
CIMON
–VIN
8709 BD
CVEE
RFBY
Figure 1. Block Diagram
For more information www.linear.com/LT8709
8709f
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LT8709.PDF ] | |
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