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PDF LT4275 Data sheet ( Hoja de datos )
| Número de pieza | LT4275 | |
| Descripción | PD Controller | |
| Fabricantes | Linear | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LT4275 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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Features
n IEEE 802.3af/at and LTPoE++™ Powered Device
(PD) Controller
n LTPoE++ Supports Power Levels Up to 90W
n LT4275A Supports All of the Following Standards:
n LTPoE++ 38.7W, 52.7W, 70W and 90W
n IEEE 802.3at 25.5W Compliant
n IEEE 802.3af Up to 13W Compliant
n LT4275B is IEEE 802.3at/af Compliant
n LT4275C is IEEE 802.3af Compliant
n 100V Absolute Maximum Input Voltage
n Wide Junction Temperature Range (–40°C to 125°C)
n Overtemperature Protection
n Integrated Signature Resistor
n External Hot Swap™ N-Channel MOSFET for Lowest
Power Dissipation and Highest System Efficiency
n Programmable Aux Power Support as Low as 9V
n Optional Support of Non-Standard Low Voltage PoE
n Available in 10-Lead MSOP and 3mm × 3mm DFN
Packages
Applications
n High Power Wireless Data Systems
n Outdoor Security Camera Equipment
n Commercial and Public Information Displays
n High Temperature Industrial Applications
LT4275
LTPoE++/PoE+/PoE
PD Controller
Description
The LT®4275 is a pin-for-pin compatible family of IEEE
802.3 and LTPoE++ powered device (PD) controllers.
The LT4275A employs a proprietary LTPoE++ classification
scheme, delivering 38.7W, 52.7W, 70W or 90W of power
at the PD RJ45 connector. The LT4275A is fully compat-
ible with IEEE 802.3. The LT4275B is an IEEE 802.3at
compliant, Type 2 (PoE+) PD delivering up to 25.5W. The
LT4275C is an IEEE 802.3af compliant, Type 1 (PoE) PD
delivering up to 13W.
The LT4275 internal charge pump provides an N-channel
MOSFET solution, eliminating a larger and more costly
P-channel MOSFET. A low RDS(ON) MOSFET also maxi-
mizes power delivery and efficiency, reduces power and
heat dissipation, and eases thermal design. Startup inrush
current is adjustable with an external capacitor. The LT4275
also includes a power good output, on-board signature
resistor, undervoltage lockout, and thermal protection. The
LT4275A/LT4275B drives a single opto-coupler to indicate
the power level of the attached PSE. Pin-selectable sup-
port for non-standard low voltage operation is provided.
Auxiliary power override is supported with the AUX pin.
The LT4275A can be configured to support all possible
LTPoE++, 802.3at and 802.3af power levels with external
component changes.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
LTPoE++ and Hot Swap are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
Typical Application
LTPoE++ 90W Powered Device Interface
VAUX (9V TO 60V)
~
DATA
PAIR ~
SPARE
PAIR
~
~
+
VPORT
–
+
–
CPD
0.1µF
RCLS
FDMC86102
3.3k
VPORT HSGATE
AUX
RCLS++
RCLASS
RCLASS++
LT4275A
GND IEEEUVLO
+
47nF
HSSRC
PWRGD
T2P
4275 TA01a
CPORT
VIN
ISOLATED
POWER
SUPPLY
RUN
+
VOUT
–
OPTO
PSE TYPE
(TO µP)
LT4275 Family
MAX DELIVERED
POWER
LTPoE++ 90W
LTPoE++ 70W
LTPoE++ 52.7W
LTPoE++ 38.7W
25.5W
13W
LT4275 GRADE
A BC
l
l
l
l
ll
l ll
4275f
1
1 page  
LT4275
Pin Functions
IEEEUVLO (Pin 1): Hot Swap Turn-on Threshold Level
Control. Connect to ground for IEEE compliant turn-on
and turn-off (UVLO) voltage thresholds. Leave open for
lower turn-on and turn-off voltage thresholds.
AUX (Pin 2): Auxiliary Sense. Assert AUX via a resistive
divider from the auxiliary power input to set the voltage
at which the auxiliary supply takes over. Asserting AUX
pulls down HSGATE, disconnects the signature resistor,
disables classification and floats the PWRGD pin. The
AUX pin sinks IAUXH when below its threshold voltage of
VAUXT to provide hysteresis. Tie to GND when not used.
RCLASS (Pin 3): Programmable PoE Classification Resis-
tor. See Table 1.
RCLASS++ (Pin 4, LT4275A Only): Programmable
LTPoE++ Classification Resistor. This pin is not connected
on the LT4275B/LT4275C. See Table 1.
GND (Pin 5): Ground Pin. Must be soldered to PCB GND.
T2P (Pin 6, LT4275A/LT4275B Only): PSE Type Indica-
tor, Open-Drain Output. T2P floats for a 13W PSE. T2P
pulls down for a 25.5W PSE. T2P pulls down at fT2P with
a 50% (typical) duty cycle to indicate the presence of an
LTPoE++ PSE. T2P is valid after PWRGD is active. This pin
is not connected on the LT4275C. See the Applications
Information section for behavior when using the AUX pin.
PWRGD (Pin 7): PowerGoodIndicator,Open-DrainOutput.
Pulls down during VCLASS and inrush.
HSSRC (Pin 8): External Hot Swap MOSFET Source. Con-
nect to source of the external MOSFET.
HSGATE (Pin 9): External Hot Swap MOSFET Gate Control,
Output. Connect to gate of the external MOSFET.
VPORT (Pin 10): PD interface upper power rail and external
Hot Swap MOSFET drain connection.
Exposed Pad (Pin 11, DFN Package Only): GND. Must
be soldered to PCB GND.
Block Diagram
VPORT
VPORT
VOLTAGE AND
CURRENT REFERENCES
PWRGD
AUX +
6.3V –
1.4V
RCLASS
+
– EN
VPORT
CONTROL
LOGIC
ON
CHARGE
PUMP
IEEEUVLO
HSGATE
VGOC HSSRC
OVERTEMP
CLASSIFICATION
LOGIC
GND
T2P
VPORT
+ 1.4V
EN –
RCLASS++
4275 BD
4275f
5
5 Page 
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
LT4275
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
10 9 8 7 6
0.497 ± 0.076
(.0196 ± .003)
REF
0.254
(.010)
DETAIL “A”
0° – 6° TYP
4.90 ± 0.152
(.193 ± .006)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
GAUGE PLANE
12345
0.53 ± 0.152
(.021 ± .006)
1.10
DETAIL “A”
0.18
(.043)
MAX
(.007)
SEATING
PLANE 0.17 – 0.27
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
(.007 – .011)
TYP
0.50
(.0197)
BSC
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.86
(.034)
REF
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MS) 0307 REV E
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
4275f
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LT4275.PDF ] | |
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