PDF PIC16F18344 Data sheet ( Hoja de datos )

Número de pieza	PIC16F18344
Descripción	Low Pin Count Microcontrollers
Fabricantes	Microchip
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No Preview Available ! PIC16(L)F18324/18344 Full-Featured, Low Pin Count Microcontrollers with XLP Description PIC16(L)F18324/18344 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals, combined with eXtreme Low Power (XLP) for a wide range of general purpose and low-power applications. The Peripheral Pin Select (PPS) functionality enables pin mapping when using the digital peripherals (CLC, CWG, CCP, PWM and communications) to add flexibility to the application design. Core Features • C Compiler Optimized RISC Architecture • Only 49 Instructions • Operating Speed: - DC – 32 MHz clock input - 125 ns minimum instruction cycle • Interrupt Capability • 16-Level Deep Hardware Stack • Up to Four 8-Bit Timers • Up to Three 16-Bit Timers • Low-Current Power-on Reset (POR) • Configurable Power-up Timer (PWRTE) • Brown-out Reset (BOR) with Fast Recovery • Low-Power BOR (LPBOR) Option • Extended Watchdog Timer (WDT) with Dedicated On-Chip Oscillator for Reliable Operation • Programmable Code Protection Memory • 7 Kbytes Program Flash Memory • 512 Bytes Data SRAM Memory • 256B of EEPROM • Direct, Indirect and Relative Addressing modes Operating Characteristics • Operating Voltage Range: - 1.8V to 3.6V (PIC16LF18324/18344) - 2.3V to 5.5V (PIC16F18324/18344) • Temperature Range: - Industrial: -40°C to 85°C - Extended: -40°C to 125°C eXtreme Low-Power (XLP) Features • Sleep mode: 40 nA @ 1.8V, typical • Watchdog Timer: 250 nA @ 1.8V, typical • Secondary Oscillator: 300 nA @ 32 kHz • Operating Current: - 8 A @ 32 kHz, 1.8V, typical - 37 A/MHz @ 1.8V, typical Power-Saving Functionality • IDLE mode: ability to put the CPU core to Sleep while internal peripherals continue operating from the system clock • DOZE mode: ability to run the CPU core slower than the system clock used by the internal peripherals • SLEEP mode: Lowest Power Consumption • Peripheral Module Disable (PMD): peripheral power disable hardware module to minimize power consumption of unused peripherals Digital Peripherals • Configurable Logic Cell (CLC): - Four CLCs - Integrated combinational and sequential logic • Complementary Waveform Generator (CWG): - Two CWGs - Rising and falling edge dead-band control - Full-bridge, half-bridge, 1-channel drive - Multiple signal sources • Capture/Compare/PWM (CCP) modules - Four CCPs - 16-bit resolution for Capture/Compare modes - 10-bit resolution for PWM mode • Pulse-Width Modulators (PWM): - Two 10-bit PWMs • Numerically Controlled Oscillator (NCO): - Precision linear frequency generator (@50% duty cycle) with 0.0001% step size of source input clock - - IRnepsuot lCutlioocnk::F0NCHOz/2<20FNCO < 32 MHz • Serial Communications: - EUSART - RS-232, RS-485, LIN compatible - Auto-Baud Detect, auto-wake-up on start - Master Synchronous Serial Port (MSSP) - SPI - I2C™, SMBus, PMBus™ compatible • Data Signal Modulator (DSM): - Modulates a carrier signal with digital data to create custom carrier synchronized output waveforms  2015 Microchip Technology Inc. Preliminary DS40001800A-page 1 1 page PIN ALLOCATION TABLES TABLE 1: 14/16-PIN ALLOCATION TABLE (PIC16(L)F18324) RA0 13 12 ANA0 — C1IN0+ — DAC1OUT — ——— — — — — — IOC Y ICDDAT/ ICSPDAT RA1 12 11 ANA1 VREF+ C1IN0- — DAC1REF+ C2IN0- — ——— — — — — — IOC Y ICDCLK/ ICSPCLK RA2 11 10 ANA2 VREF- — — DAC1REF- — T0CKI(1) CCP3(1) — CWG1IN(1) — — — — INT(1) Y — CWG2IN(1) IOC RA3 4 3— — — — — — ——— — — — — — IOC Y MCLR VPP RA4 3 2 ANA4 — — — — — T1G(1) — SOSCO — — — — — — IOC Y CLKOUT OSC2 RA5 2 1 ANA5 — — — — — T1CKI(1) — SOSCIN SOSCI — — — — CLCIN3(1) — IOC Y CLKIN OSC1 RC0 10 9 ANC0 — C2IN0+ — — — T5CKI(1) — — — SCK1(1) — — — IOC Y — SCL1(1,3,4) RC1 9 8 ANC1 — C1IN1- C2IN1- — — — — CCP4(1) — — SDI1(1) — CLCIN2(1) — IOC Y — SDA1(1,3,4) RC2 8 7 ANC2 — C1IN2- C2IN2- — — MDCIN1(1) — — — — — — — — IOC Y — RC3 7 6 ANC3 — C1IN3- C2IN3- — — MDMIN(1) T5G(1) CCP2(1) — — SS1(1) — CLCIN0(1) — IOC Y — RC4 6 5 ANC4 — — — — — T3G(1) — — — — — CLCIN1(1) — IOC Y — RC5 5 4 ANC5 — — — — MDCIN2(1) T3CKI(1) CCP1(1) — — — RX(1) — DT(1,3) — IOC Y — VDD 1 16 — — — — — — ——— — — — — — — — VDD VSS 14 13 — — — — — — ——— — — — — — — — VSS Note 1: 2: 3: 4: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C™ logic levels; clock and data signals may be assigned to any of these pins. Assignments to the other pins (e.g., RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register. 5 Page PIC16(L)F18324/18344 1.0 DEVICE OVERVIEW The PIC16(L)F18324/18344 devices are described within this data sheet. PIC16(L)F18324 is available in 14-pin PDIP, SOIC, TSSOP and 16-pin UQFN packages. PIC16(L)F18344 is available in 20-pin PDIP, SOIC, SSOP and UQFN packages. See Section 37.0 “Packaging Information” for further packaging information. Figure 1-1 shows a block diagram of the PIC16(L)F18324/18344 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device. TABLE 1-1: DEVICE PERIPHERAL SUMMARY Peripheral Analog-to-Digital Converter (ADC) ●● Temperature Indicator ●● Digital-to-Analog Converter (DAC) DAC1 ● ● Fixed Voltage Reference (FVR) ADCFVR ● ● CDAFVR ● ● Digital Signal Modulator (DSM) DSM1 ● ● Numerically Controlled Oscillator (NCO) NCO1 ● ● Capture/Compare/PWM (CCP/ECCP) Modules CCP1 ● ● CCP2 ● ● CCP3 ● ● CCP4 ● ● Comparators C1 ● ● C2 ● ● Complementary Waveform Generator (CWG) CWG1 ● ● CWG2 ● ● Configurable Logic Cell (CLC) CLC1 ● ● CLC2 ● ● CLC3 ● ● CLC4 ● ● Enhanced Universal Synchronous/Asynchronous Receiver/ Transmitter (EUSART) EUSART1 ● ● TABLE 1-1: DEVICE PERIPHERAL SUMMARY (CONTINUED) Peripheral Master Synchronous Serial Port (MSSP) MSSP1 Pulse-Width Modulator (PWM) PWM5 PWM6 Timers Timer0 Timer1 Timer2 Timer3 Timer4 Timer5 Timer6 ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ●  2015 Microchip Technology Inc. Preliminary DS40001800A-page 11 11 Page

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