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PDF MAX3825 Data sheet ( Hoja de datos )
| Número de pieza | MAX3825 | |
| Descripción | 2.5Gbps Quad Transimpedance Amplifier | |
| Fabricantes | Maxim Integrated | |
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19-1855 Rev 0; 11/00
+3.3V, 2.5Gbps Quad Transimpedance Amplifier
for System Interconnects
General Description
The MAX3825 is a quad transimpedance amplifier (TIA)
intended for 2.5Gbps system interconnect applications.
Each of the four channels converts a small photodiode
current to a measurable differential voltage with a tran-
simpedance gain of 3.7kΩ. The circuit features
460nARMS of input-referred noise per channel corre-
sponding to an optical input sensitivity of -22.3dBm
(BER ≤ 1 × 10-14). The quad transimpedance amplifier
has 20ps of deterministic jitter and a 2.4GHz small-sig-
nal bandwidth. The MAX3825 is optimized for use with
a quad PIN photodetector array with a standard fiber
pitch of 250µm.
The MAX3825 operates from a single +3.3V supply
over a 0°C to +85°C temperature range. With a +3.3V
supply, each channel dissipates 93mW of power. A DC
cancellation circuit on each channel provides a true dif-
ferential output swing over a wide range of input cur-
rents.
Each channel has an independent supply and ground
to allow all or any combination of channels to be con-
nected. This device is available in dice only.
Typical Operating Circuit appears at end of data sheet.
Features
o Single +3.3V Supply
o 93mW per Channel Power Dissipation
o 460nARMS Input-Referred Noise
o 20ps Deterministic Jitter
o 2.4GHz Small-Signal Bandwidth
o No External Compensation
o 40dB Power-Supply Rejection Ratio
o Compact Die with 250µm Channel Pitch
o 100Ω Differential Output Impedance
Ordering Information
PART
MAX3825U/D
TEMP. RANGE
0°C to +85°C
PIN-PACKAGE
Dice*
*Dice are designed to operate with a 0°C to +120°C junction
temperature, but are tested and guaranteed only at TA = +25°C.
Applications
System Interconnects
SDH/SONET
Backplanes
Dense Digital Cross-
Connects
ATM Switching
Networks
High-Speed Parallel
Optical Links
Chip Topography/Pad Configuration
VCCO1 OUT1+ OUT1- VCCO1 VCCO2 OUT2+ OUT2- VCCO2 VCCO3 OUT3+ OUT3- VCCO3 VCCO4 OUT4+ OUT4-VCCO4
N.C. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
GNDO1 37
20 GNDO4
GNDO2 38
GNDF 39
GNDI2
VCCI2
40
41
VCCI1 42
GNDI1 43
VCCFILT 44
12
3
N.C. N.C. FILTER
4 5 6 7 8 9 10 11
IN1 FILT1 IN2 FILT2 IN3 FILT3 IN4 FILT4
19 GNDO3
18 ENABLE
17 GNDI3
16 VCCI3
15 VCCI4
14 GNDI4
12 13
N.C. N.C.
________________________________________________________________ Maxim Integrated Products 1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
+3.3V, 2.5Gbps Quad Transimpedance Amplifier
for System Interconnects
Functional Diagram
D2
D1
RF = 1.3kΩ
VCCI_
IN_
GNDI_
Q1
C1
R5
VCCI_
PARAPHASE
AMP
VCC FILT
720Ω
FILT_
VCCO_
R1
50Ω OUT_+
Q2
VCCO_
R2
50Ω
OUT_-
Q3
GNDI_
Q4
GNDI_
Q5 REFERENCE
AMP
DC
CANCELLATION
AMP
R3
R4
MAX3825
ENABLE
Figure 1. Functional Diagram for One Channel of the MAX3825
Detailed Description
The MAX3825 quad TIA circuit is designed for 2.5Gbps
SONET/SDH applications. It comprises a transimped-
ance amplifier, a paraphase amplifier with CML out-
puts, and a DC cancellation loop to reduce pulse-width
distortion (Figure 1).
Transimpedance Amplifier
The signal current at IN_ flows into the summing node
of a high-gain amplifier. Shunt feedback through RF
converts this current to a voltage with a gain of 1300Ω.
Diodes D1 and D2 clamp the output voltage for large
input currents. GNDI_ is a direct connection to the emit-
ter of the input transistor and must be connected
directly to the photodetector AC ground return for best
performance.
GNDO_
DC Cancellation Loop
The DC cancellation loop removes the DC component
of the input signal by using low-frequency feedback.
This feature centers the signal within the MAX3825’s
dynamic range, reducing pulse-width distortion.
The output of the paraphrase amplifier is sensed through
resistors R3 and R4 and then filtered, amplified, and fed
back to the base of transistor Q4. The transistor draws
the DC component of the input signal away from the
transimpedance amplifier’s summing node.
The MAX3825 DC cancellation loop is internally com-
pensated and does not require external capacitors in
most 2.5Gbps applications. The DC cancellation loop
for all channels can be disabled by connecting
ENABLE to the positive supply (VCC). ENABLE is inter-
_______________________________________________________________________________________ 5
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MAX3825.PDF ] | |
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