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PDF ALM-GP001 Data sheet ( Hoja de datos )
| Número de pieza | ALM-GP001 | |
| Descripción | GPS Filter-LNA-Filter Front-End Module | |
| Fabricantes | AVAGO | |
| Logotipo |  |
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ALM-GP001
GPS Filter-LNA-Filter Front-End Module
Data Sheet
Description
Avago Technologies’ ALM-GP001 is an ultra low-noise GPS
front-end module that combines a low-noise amplifier
(LNA) with GPS FBAR filters. The LNA uses Avago Tech-
nologies’ proprietary GaAs Enhancement-mode pHEMT
process to achieve high gain with very low noise figure
and high linearity. Noise figure distribution is very tightly
controlled. A CMOS-compatible shutdown pin is included
either for turning the LNA on/off, or for current adjust-
ment. The integrated filter utilizes an Avago Technologies’
leading-edge FBAR filter for exceptional rejection at
Cellular, DCS, PCS and WLAN band frequencies. Bypass
functionality with an external RF switch is possible with
separate RF switching.
The low noise figure and high gain, coupled with low cur-
rent consumption make it suitable for use in critical low-
power GPS applications or during low-battery situations.
Component Image
Surface Mount (3.0 x 2.5 x 1) mm3 12-lead MCOB
RF In (pin 1)
Gnd Vsd Gnd
(pin 12) (pin 11) (pin 10)
Vdd (pin 9)
Gnd (pin 2)
Gnd (pin 3)
GP001
YMXXXX
Gnd Gnd Gnd
(pin 4) (pin 5) (pin 6)
RF Out (pin 8)
Gnd (pin 7)
TOP VIEW
Vdd (pin 9)
Gnd Vsd Gnd
(pin 10) (pin 11) (pin 12)
RF In (pin 1)
Features
• Operating temperature range -40 to +85 °C
• Very Low Noise Figure: 1.26 dB typ.
• Exceptional Cell/DCS/PCS/WLAN-Band rejection
• Advanced GaAs E-pHEMT & FBAR Technology
• Low external component count.
• CMOS compatible shutdown pin (SD)
• ESD: > 3kV at RFin pin
• Adjustable bias current via single external resistor/
voltage
• Useable down to 1.8V supply voltage
• Small package dimension: 3.0(L)x2.5(W)x1(H) mm3
• Meets MSL3, Lead-free and halogen free
Specifications (Typical performance @ 25°C)
At 1.575GHz, Vdd = 2.7V, Idd = 7.5mA
• Gain = 14.2 dB
• NF = 1.26 dB
• IIP3 = +5 dBm, IP1dB = +2 dBm
• S11 = -9 dB, S22 =-12 dB
• Low-Band Rejection (824 – 928MHz): 89 dBc
• High-Band Rejection (1710 – 1980MHz): 80 dBc
• WLAN-Band Rejection (2400 – 2500MHz): 72 dBc
Application
• GPS Front-end Module
Application Circuit
Vdd = +2.7V
Vsd C1 C2
RF Out (pin 8)
Gnd (pin 2)
Gnd (pin 7)
Gnd Gnd Gnd
(pin 6) (pin 5) (pin 4)
Gnd (pin 3)
BOTTOM VIEW
Note:
Package marking provides orientation and identification
“GP001” =
Product Code
“Y” = Year of manufacture
“M” = Month of manufacture
“XXXX” = Last 4 digit of lot number
RFin
RFout
Attention: Observe precautions for
handling electrostatic sensitive devices.
RF In (Pin 1) to GND: ESD Human Body Model = 3 kV
All other Pins : ESD Machine Model = 50 V
: ESD Human Body Model = 300 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
1 page  
Vdd=+2.7V
R1*
Vsd
C3*
R2*
C1 0.1uF
L1*
C2
47pF
Vdd
RFin RFout
Figure 2. Application Circuit
* optional, see notes below
Notes:
• The ALM-GP001 can be operated with supply voltage (Vdd) from 1.5V to 2.85V. Vsd can operate from 1V to Vdd.
• The module is fully matched at the input and output RF pins. The RFinput pin is connected directly to a shunt inductor to ground. As such a DC
blocking capacitor is required if DC voltages are present. The RFoutput pin is already DC-blocked by the internal filter inside the module.
• Best noise performance is obtained using high-Q wirewound inductors. This circuit demonstrates that low noise figures are obtainable with
standard 0402 chip inductors.
• C1 and C2 are bypass capacitors for RF and low frequency stability and linearity .
• L1 and R1 isolates the demoboard from external disturbances during measurement. It is not needed in actual application. Likewise, C3 mitigate the
effect of external noise pickup on the Vsd line. This component are not required in actual operation. Minimal component operation is as shown in
the schematic on page 1.
• Bias control is achieved by either varying the Vsd voltage with/ without R2, or fixing the Vsd voltage to Vdd and adjusting R2 for the desired current.
5
5 Page 
ALM-GP001 module with differential output
A differential output can be implemented for the ALM-GP001 using the schematic shown below. Suggested component
values are listed in Table 3. C1, C2 and L1, L2 are to convert the single-ended output to differential outputs while C3, C4
and L3 provide matching to 100 ohm differential impedance.
Vsd Vdd
12 ohm
0.1uF
BBIIAASS C1
L2
C2
L1
Figure 24. Proposed Balun design for ALM-GP001
Table 3. Components table for proposed balun design
Circuit Symbol Size Description
C1 0402 GRM1555C1H1R5CZ01 - 1.5pF (Murata)
C2 0402 GRM1555C1H1R5CZ01 - 1.5pF (Murata)
C3 0402 GRM1555C1H101JZ01 – 100pF (Murata)
C4 0402 GRM1555C1H101JZ01 – 100pF (Murata)
L1 0402 LQG15HN6N2S02B – 6.2nH (Murata)
L2 0402 LQG15HN6N2S02B – 6.2nH (Murata)
L3 0402 LQG15HN56NJ02 – 56nH (Murata)
C3
L3
C4
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ALM-GP001.PDF ] | |
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