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Número de pieza NX5P1100
Descripción Logic controlled high-side power switch
Fabricantes NXP Semiconductors 
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NX5P1100
Logic controlled high-side power switch
Rev. 1 — 21 March 2014
Product data sheet
1. General description
The NX5P1100 is an advanced power switch and ESD-protection device for USB OTG
applications. It includes under voltage and over voltage lockout, over-current,
over-temperature, reverse bias and in-rush current protection circuits. These circuits are
designed to isolate a VBUS OTG voltage source from a VBUS interface pin automatically
when a fault condition occurs. The device features two power switch terminals, one input
(VINT) and one output (VBUS). It has a current limit input (ILIM) for defining the
over-current and in-rush current limit. A voltage detect output (VDET) is used to determine
when VINT is in the correct voltage range. An open-drain fault output (FAULT) indicates
when a fault condition has occurred, and an enable input (EN) controls the state of the
switch. When EN is set LOW the device enters a low-power mode, disabling all protection
circuits except the undervoltage lockout. The low-power mode can be entered at anytime
unless the over temperature protection circuit has been triggered.
Designed for operation from 3 V to 5.5 V, it is used in power domain isolation applications
to protect from out of range operation. The enable input includes integrated logic level
translation making the device compatible with lower voltage processors and controllers.
2. Features and benefits
Wide supply voltage range from 3 V to 5.5 V
30 V tolerant on VBUS
ISW maximum 1 A continuous current
Very low ON resistance: 100 m(maximum) at a supply voltage of 4.0 V
Low-power mode (ground current 20 A typical)
1.8 V control logic
Soft start turn-on slew rate
Protection circuitry
Over-temperature protection
Over-current protection with low current output mode
Reverse bias current/Back drive protection
Overvoltage lockout
Undervoltage lockout
Analog voltage limited VBUS monitor path
ESD protection:
HBM ANSI/ESDA/JEDEC JDS-001 Class 2 exceeds 2 kV
CDM AEC standard Q100-011 category C6 exceeds 1 kV
IEC61000-4-2 contact discharge exceeds 8 kV for pins VBUS, D, D+ and ID
Specified from 40 C to +85 C

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NX5P1100 pdf
NXP Semiconductors
NX5P1100
Logic controlled high-side power switch
8.3 VDET output
VDET is an analog output that allows a controller to monitor the voltage level on VBUS.
8.4 Undervoltage lockout (UVLO)
When VINT < 3.2 V, the UVLO circuit is triggered. It disables the N-channel MOSFET sets
the FAULT output LOW and the device enters low-power mode. Once VINT > 3.2 V, the
EN pin controls the state of the N-channel MOSFET. The UVLO circuit remains active in
low-power mode.
8.5 Overvoltage lockout (OVLO)
When EN is HIGH and VINT > 5.75 V, the OVLO circuit is triggered. It disables the
N-channel MOSFET and sets the FAULT output LOW. The OVLO circuit is disabled in
low-power mode and does not influence the FAULT output state. If the OVLO circuit is
triggered, setting the EN pin LOW returns the device to low-power mode.
8.6 Over-current protection (OCP)
If either of these two conditions occur for longer than 8 ms, the OCP circuit is triggered.
1. Current through the N-channel MOSFET exceeds Itrig.
2. VBUS < VINT 200 mV.
During the 8 ms trigger delay, the maximum current is clamped at Iocp. The OCP disables
the N-channel MOSFET; supplies VBUS from the 10 mA current source (IO), and sets
FAULT LOW. When VINT > VBUS > VINT - 200 mV for 20 s, the OCP circuit is disabled.
EN controls the state of the N-channel MOSFET, the 10 mA current source is
disconnected and FAULT is set high impedance. If the OCP circuit is active, setting the
EN pin LOW returns the device to low-power mode. (see Figure 23, Figure 24, Figure 25,
Figure 26)
8.7 ILIM
The OCP trigger value Itrig, is set using an external resistor RILIM connected to the ILIM pin
(see Figure 6). When EN is HIGH and ILIM is grounded, VBUS is supplied by the 10 mA
current source and FAULT is set LOW.
8.8 Over-temperature protection (OTP)
When EN is HIGH, if the device temperature exceeds 125 C, the OTP circuit is triggered.
It disables the N-channel MOSFET and sets FAULT LOW. Any transition on EN has no
effect. Once the device temperature decreases to below 115 C the device returns to the
defined state. The OTP circuit is disabled in low-power mode. If the OTP circuit is active,
setting the EN pin LOW does not return the device to low-power mode.
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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NX5P1100 arduino
NXP Semiconductors
NX5P1100
Logic controlled high-side power switch

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(1) VI(VINT) = 5.5 V
(2) VI(VINT) = 4.0 V
Fig 13. Typical ON resistance versus temperature



     
9,17 9
(1) Tamb = 85 C
(2) Tamb = 25 C
(3) Tamb = 40 C
Fig 14. Typical ON resistance versus input voltage
14. Dynamic characteristics
Table 11. Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 16.
VI(VINT) = 4.0 V to 5.5 V.
Symbol Parameter
Conditions
Tamb = 25 C
Tamb = 40 C to +85 C
Unit
Min Typ Max
Min
Max
ten enable time
EN to VBUS; see Figure 15
- 0.18 -
0.14
- ms
tdis disable time
EN to VBUS; see Figure 15
- 1.5 -
-
- ms
ton turn-on time
EN to VBUS; see Figure 15
- 0.63
-
0.52
- ms
toff turn-off time
EN to VBUS; see Figure 15
- 34.5
-
-
- ms
tTLH LOW to HIGH
VBUS; see Figure 15
output transition
time
- 0.39
-
0.16
- ms
tTHL HIGH to LOW
VBUS; see Figure 15
output transition
time
- 33
-
-
- ms
tdegl deglitch time
VINT; while enabled;
see Figure 23
[1] - 8
-
-
- ms
[1] Guarantee by design.
NX5P1100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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