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PDF SL18861DI Data sheet ( Hoja de datos )
| Número de pieza | SL18861DI | |
| Descripción | 3-Channel Clock Distribution Buffer | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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SL18861DI
3-Channel Clock Distribution Buffer
Key Features
• Low current consumption:
- 2.7mA-typ (VDD=1.8V, CL=0)
• 1.70V to 3.65V power supply operation
• 10MHz to 52MHz CLKIN range
• Supports LVCMOS or Sine Inputs
• Supports 3 single-ended LVCMOS square wave or
clipped sine wave outputs
• OE1/2/3 functions for each CLKOUT1/2/3 outputs
• OE_OSC control pin to enable external TCXO/XO
• Ultra-Low phase noise
• Ultra low standby current
• 10-pin TDFN package (1.4x2.0x0.75 mm)
• Industrial -40 ºC to 85 ºC temperature range
Application
• Smart Mobile Handsets
• Multi-mode RF Clock Distribution
• Baseband Peripheral Clock Distribution
Description
The SL18861DI product is a high performance 3 output
clock distribution buffer and provides 3 outputs from a
single input clock by using SLI proprietary low phase
noise and low power dissipation circuit design.
The SL18861DI can be used in baseband mobile RF
applications including WLAN, Bluetooth and DVB-H as an
input clock reference. The product designed to isolate
each device driven by their clock outputs to minimize
interference between these devices.
Each of the clock buffer outputs can be individually
disabled by using OE1/2/3 control pins to reduce the
power consumption if the connected device does not need
the clock. The device operates from single power supply
from 1.70V to 3.65V and from -40 ºC to 85 ºC.
Benefits
• Fast Time-to-market
• Cost Reduction
• Low Power Dissipation
• Low Phase Noise
Block Diagram
CLKIN 3
OE_OSC 4
8 CLKOUT1
9 CLKOUT2
CONTROL LOGIC
675
OE1
OE2
OE3
10 CLKOUT3
2
VDD
1
VSS
Rev 1.2, December 21 , 2010
2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500
1+(512) 416-9669
Page 1 of 12
www.silabs.com
1 page  
SL18861DI
DC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 2.5V+/- 10% and Operation Temperature Range -40 to +85°C
Description
Symbol
Condition
Operating Voltage
VDD Operation range, 2.5V+/10%
Operating Temperature
TA I-Grade
Input Low Voltage
VIL CMOS Level, Pins 3,5, 6 and 7
Input High Voltage
Output High Voltage
VIH
VOH
CMOS Level, Pins 3,5, 6 and 7
IOH=-4mA , Pins 4, 8, 9 and 10
Output Low Voltage
Input Leakage Current
Input Leakage Current
VOL
ILH
ILL
IOL=-4mA, Pins 4, 8, 9 and 10
VIN=VDD, Pins 5, 6 and 7
VIN=GND, Pins 5, 6 and 7
Pull-Down Resistor
Operating Supply Current
Operating Supply Current
Input Capacitance
Load Capacitance
RPD
IDD1
IDD2
CIN
CL
Pins 5, 6 and 7
CLKIN=26MHz,
OE1=OE2=OE3=1, CL=0
OE1=OE2=OE3=0
CLKIN=Low or High
Pins 5, 6 and 7
CLKOUT1/2/3, Pins 8, 9 and 10
Min
2.25
-40
VSS
0.7VDD
VDD-0.4
-
-30
-15
100
-
-
-
-
Typ
2.50
25
-
-
-
-
-
-
150
3.0
-
3
10
Max
2.75
85
0.3VDD
VDD
-
0.4
30
15
250
-
Unit
V
ºC
V
V
V
V
μA
μA
kΩ
mA
1.5 µA
5 pF
20 pF
AC Electrical Characteristics (I-Grade)
Unless otherwise stated VDD= 2.5V+/- 10% and Operation Temperature Range -40 to +85°C
Parameter
Symbol
Condition
Min Typ Max
Unit
Input Clock Range
Output Clock Range
Input Clock Voltage
Swing Level
CLKIN
CLKOUT
External Clock, CMOS square wave
or sine wave
External Clock, CMOS square wave
CLKOUT1/2/3
VINpp VDD=2.5V
10 26.000 52
10 26.000
1.0 1.2
52
-
MHz
MHz
Vpp
Input Duty Cycle
DCIN CLKIN, Pin 3
30 50 70 %
VDD=1.8, CL=10pF, measured from
Output Clock Rise Time
tr 10 to 90% of VDD, Pins 4, 8, 9 and
-
2.0 4.00
ns
10
Output Clock Fall Time
VDD=1.8, CL=10pF, measured from
tf 10 to 90% of VDD, Pins 4, 8, 9 and
-
10
2.0 4.00
ns
Additive Phase Noise
APN-1
CLKIN=26MHz and 1 kHz offset
CLKOUT1/2/3
- -142 - dBc/Hz
Rev 1.2, December 21 , 2010
Page 5 of 12
5 Page 
Package Outline and Package Dimensions
10-Pin TDFN Package (1.4x2.0x0.75 mm)
SL18861DI
Top View
Side View
Bottom View
Side View
Rev 1.2, December 21 , 2010
Page 11 of 12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet SL18861DI.PDF ] | |
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