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PDF SI53340 Data sheet ( Hoja de datos )
| Número de pieza | SI53340 | |
| Descripción | 1:4 LOW-JITTER LVDS CLOCK BUFFER | |
| Fabricantes | Silicon Laboratories | |
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Si53340
1:4 LOW-JITTER LVDS CLOCK BUFFER WITH 2:1 INPUT MUX
Features
4 LVDS outputs
VDD: 1.8 / 2.5 / 3.3 V
Ultra-low additive jitter: 45 fs rms 16-QFN (3 mm x 3 mm)
Wide frequency range: dc to
1250 MHz
2:1 input mux
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Universal input stage accepts
differential or LVCMOS clock
Applications
High-speed clock distribution Storage
Ethernet switch/router
Telecom
Optical Transport Network (OTN) Industrial
SONET/SDH
Servers
PCI Express Gen 1/2/3
Backplane clock distribution
Description
The Si53340 is an ultra low jitter four output LVDS buffer. The Si53340
features a 2:1 input mux, making it ideal for redundant clocking
applications. Utilizing Silicon Laboratories’ advanced fan-out clock
technology, the Si53340 guarantees low additive jitter, low skew, and low
propagation delay variability from dc to 1250 MHz.
The Si53340 features minimal cross-talk and excellent supply noise
rejection, simplifying low jitter clock distribution in noisy environments.
Functional Block Diagram
Ordering Information:
See page 19.
Pin Assignments
Patents pending
Rev. 1.0 7/15
Copyright © 2015 by Silicon Laboratories
Si53340
1 page  
Si53340
Table 6. Additive Jitter, Differential Clock Input
VDD
Input1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)3
Freq
(MHz)
Clock Format
Amplitude
VIN
(Single-Ended,
Peak-to-Peak)
Differential Clock Format
20%-80% Slew
Rate (V/ns)
Typ
Max
3.3 725 Differential
0.15
0.637
LVDS
50 65
3.3 156.25 Differential
0.5
0.458
LVDS
150 200
2.5 725 Differential
0.15
0.637
LVDS
50 65
2.5 156.25 Differential
0.5
0.458
LVDS
145 195
Notes:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2. AC-coupled differential inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1.
Table 7. Additive Jitter, Single-Ended Clock Input
VDD
Input1,2
Output
Additive Jitter
(fs rms, 12 kHz to
20 MHz)3
Freq
(MHz)
Clock Format
Amplitude
VIN
(single-ended,
peak to peak)
SE 20%-80%
Slew Rate
(V/ns)
Clock Format
Typ
Max
3.3 156.25 Single-ended
2.18
1
LVDS
150 200
2.5 156.25 Single-ended
2.18
1
LVDS
145 195
Notes:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2. DC-coupled single-ended inputs.
3. Measured differentially using a balun at the phase noise analyzer input (see Figure 1).
Figure 1. Differential Measurement Method Using a Balun
Rev. 1.0
5
5 Page 
2.5. AC Timing Waveforms
Si53340
Figure 7. AC Waveforms
Rev. 1.0
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet SI53340.PDF ] | |
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