PDF SI53108 Data sheet ( Hoja de datos )

Número de pieza	SI53108
Descripción	DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER
Fabricantes	Silicon Laboratories
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No Preview Available ! Si53108 DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER Features  Eight 0.7 V low-power, push-pull,  1.05 to 3.3 V power supply HCSL-compatible PCIe Gen 3 voltage outputs  Low phase jitter (Intel QPI, PCIe  Individual OE HW pins for each Gen 1/2/3/4 common clock output clock compliant  100 MHz /133 MHz PLL operation, supports PCIe and QPI  SMBus address is 0xD8  PLL or bypass mode  Spread spectrum tolerable  Gen 3 SRNS Compliant  Industrial Temperature: –40 to 85 °C  48-pin QFN  For higher output devices or variations of this device, contact Silicon Labs Applications  Server  Storage  Datacenter  Enterprise Switches and Routers Ordering Information: See page 32. Patents pending Description The Si53108 is a low-power, 8-output, differential clock buffer that meets all of the performance requirements of the Intel DB800ZL specification. The device is optimized for distributing reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output has a dedicated hardware output enable pin for maximum flexibility and power savings. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. Rev. 1.2 12/15 Copyright © 2015 by Silicon Laboratories Si53108 1 page Si53108 Table 3. Clock Input Parameters TA = –40 to 85 °C; supply voltage VDD = 3.3 V ±5% Parameter Input Frequency Symbol FIN Input High Voltage- CLK_IN VIHDIF Input Low Voltage- CLK_IN VILDIF Input Common Mode Voltage - CLK_IN Input Amplitude- CLK_IN Input Slew Rate- CLK_IN Input Leakage Current Input Duty Cycle VCOM VSwing IDDVDDAPD IIN dtin Input Jitter, Cycle-Cycle Input SS Modulation Fre- quency JDIFIN fMODIN Test Condition Bypass Mode PLL Mode, 100 MHz PLL Mode, 133.33 MHz Differential inputs single-ended measurement Differential inputs single-ended measurement Common Mode Voltage Input Peak to Peak Measured differentially VIN = VDD, VIN = GND Measured from differential waveform Differential measurement Triangle Wave Modulation Min Typ Max 33 — 150 90 100 110 120 133.33 147 600 800 1150 VSS –300 0 300 — 300 1000 300 — 1450 0.4 — 8 –5 — 5 45 — 55 0 — 125 30 — 33 Unit MHz MHz MHz mV mV mV V/ns A % ps kHz Table 4. Current Consumption TA = –40 to 85 °C; supply voltage VDD = 3.3 V ±5% Parameter Symbol Test Condition Min Typ Max Unit Operating Current IDDVDD IDDVDDA Power Down Current IDDVDDPD IDDVDDAPD 133 MHz, VDD Rail 133 MHz, VDDA + VDDR, PLL Mode Power Down, VDD Rail Power Down, VDDA Rail — — — — 79 90 mA 14 20 mA 1 1.5 mA 4 8 mA Rev. 1.2 5 5 Page Si53108 Table 9. DIF 0.7 V AC Timing Characteristics (–0.5% Spread Spectrum Mode) Parameter Symbol CLK 100 MHz, 133 MHz Min Clock Stabilization Time TSTAB Long Term Accuracy LACC Absolute Host CLK Period (100 MHz) TABS Absolute Host CLK Period (133 MHz) TABS Edge _rate Edge _rate — — 9.94900 7.44925 1.0 Typ Max 1.8 100 10.10126 7.58845 4.0 Rise/Fall Matching Voltage High (typ 0.70 V) Voltage Low (typ 0.0 V) Maximum Voltage Absolute Crossing Point Voltages TRISE_MAT/ TFALL_MAT VHIGH VLOW VMAX VCROSS(a bs) — 660 –150 — 300 20 850 150 1150 550 Relative Crossing Point Voltages VCROSS(re l) Calc Calc Total Variation of Vcross Over All Edges Cycle-to-Cycle Jitter Duty Cycle Total ∆ VCROSS TCCJITTER Duty Cycle — 45 140 50 55 Maximum Voltage (Overshoot) Maximum Voltage (Undershoot) Vovs Vuds — — VHigh + 0.3 VLow – 0.3 Unit ms ppm ns ns V/ns % mV mV mV mV mV mV ps % V V Notes 22 4,8,16 4,5,8 4,5,8 2,4,8 4,7,19,21 4,7,10 4,7,11 7 1,3,4,7,14 4,6,7,14 4,7,15 4,8,20 4,8 4,7,12 4,7,13 Rev. 1.2 11 11 Page

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