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PDF SI53106 Data sheet ( Hoja de datos )
| Número de pieza | SI53106 | |
| Descripción | SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si53106
SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER
Features
Six 0.7 V low-power, push-pull, Low phase jitter (Intel QPI, PCIe
HCSL-compatible PCIe Gen 3 Gen 1/2/3/4 common clock
outputs
compliant
Individual OE HW pins for each Gen 3 SRNS Compliant
output clock
PLL or bypass mode
100 MHz /133 MHz PLL
Spread spectrum tolerable
operation, supports PCIe and
QPI
PLL bandwidth SW SMBUS
programming overrides the latch
value from HW pin
1.05 to 3.3 V I/O supply voltage
50 ps output-to-output skew
Industrial Temperature:
–40 to 85 °C
SMBus address configurable to
allow multiple buffers in a single
40-pin QFN
For higher output devices or
control network 3.3 V supply
variations of this device, contact
voltage operation
Silicon Labs
Ordering Information:
See page 29.
Patents pending
Applications
Server
Storage
Datacenter
Enterprise Switches and Routers
Description
The Si53106 is a low-power, 6-output, differential clock buffer that meets
all of the performance requirements of the Intel DB1200ZL specification.
The device is optimized for distributing reference clocks for Intel®
QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4,
SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI)
applications. The VCO of the device is optimized to support 100 MHz and
133 MHz operation. Each differential output has a dedicated hardware
output enable pin for maximum flexibility and power savings. Measuring
PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter
Tool. Download it for free at www.silabs.com/pcie-learningcenter.
Rev. 1.2 12/15
Copyright © 2015 by Silicon Laboratories
Si53106
1 page  
Si53106
Table 3. Output Skew, PLL Bandwidth and Peaking
TA = –40 to 85 °C; supply voltage VDD = 3.3 V ±5%
Parameter
Test Condition
Min Typ Max Unit
CLK_IN, DIF[x:0]
Input-to-Output Delay in PLL Mode
Nominal Value1,2,3,4
–100 –15 100 ps
CLK_IN, DIF[x:0]
Input-to-Output Delay in Bypass Mode
\Nominal Value2,4,5
2.5 3.6 4.5 ns
CLK_IN, DIF[x:0]
Input-to-Output Delay Variation in PLL mode
Over voltage and temperature2,4,5
–100
39
100
ps
CLK_IN, DIF[x:0] Input-to-Output Delay Variation in Bypass Mode –250
3.7
250
ps
Over voltage and temperature2,4,5
DIF[11:0]
PLL Jitter Peaking
PLL Jitter Peaking
Output-to-Output Skew across all 6 Outputs
(Common to Bypass and PLL Mode)1,2,3,4,5
(HBW_BYPASS_LBW = 0)6
(HBW_BYPASS_LBW = 1)6
0 20 50 ps
— 0.4 2.0 dB
— 0.1 2.5 dB
PLL Bandwidth
PLL Bandwidth
(HBW_BYPASS_LBW = 0)7
(HBW_BYPASS_LBW = 1)7
— 0.7 1.4 MHz
— 2 4 MHz
Notes:
1. Measured into fixed 2 pF load cap. Input-to-output skew is measured at the first output edge following the
corresponding input.
2. Measured from differential cross-point to differential cross-point.
3. This parameter is deterministic for a given device.
4. Measured with scope averaging on to find mean value.
5. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created
by it.
6. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL
jitter peaking.
7. Measured at 3 db down or half power point.
Rev. 1.2
5
5 Page 
Si53106
Table 7. Clock Periods Differential Clock Outputs with SSC Disabled
SSC ON
Center
Freq, MHz
1 Clock
–C–C
Jitter
AbsPer
Min
Measurement Window
1 µs
0.1 s
0.1 s
0.1 s
1 µs
–SSC
Short
Term AVG
Min
–ppm
Long
Term AVG
Min
0 ppm
Period
Nominal
+ppm
Long
Term AVG
Max
+SSC
Short
Term AVG
Max
1 Clock
+C–C
Jitter
AbsPer
Max
100.00 9.94900
9.99900 10.00000 10.00100
10.05100
133.33 7.44925
7.49925 7.50000 7.50075
7.55075
Unit
ns
ns
Table 8. Clock Periods Differential Clock Outputs with SSC Enabled
SSC ON
Center
Freq, MHz
1 Clock
–C–C
Jitter
AbsPer
Min
Measurement Window
1 µs
0.1 s
0.1 s
0.1 s
1 µs
–SSC
Short
Term AVG
Min
–ppm
Long
Term AVG
Min
0 ppm
Period
Nominal
+ppm
Long
Term AVG
Max
+SSC
Short
Term AVG
Max
1 Clock
+C–C
Jitter
AbsPer
Max
99.75
9.94900 9.99900 10.02406 10.02506 10.02607 10.05126 10.10126
133.33 7.44925 7.49925 7.51805 7.51880 7.51955 7.53845 7.58845
Unit
ns
ns
Table 9. Absolute Maximum Ratings
Parameter
3.3 V Core Supply Voltage1
3.3 V I/O Supply Voltage1
3.3 V Input High Voltage1,2
3.3 V Input Low Voltage1
Storage Temperature1
Input ESD protection3
Symbol
VDD/VDD_A
VDD_IO
VIH
VIL
ts
ESD
Min
—
—
—
−0.5
–65
2000
Max
4.6
4.6
4.6
—
150
—
Notes:
1. Consult manufacturer regarding extended operation in excess of normal dc operating parameters.
2. Maximum VIH is not to exceed maximum VDD.
3. Human body model.
Unit
V
V
V
V
°C
V
Rev. 1.2
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI53106.PDF ] | |
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