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PDF SI53019-A01A Data sheet ( Hoja de datos )
| Número de pieza | SI53019-A01A | |
| Descripción | 19-OUTPUT PCIE GEN 3 BUFFER | |
| Fabricantes | Silicon Laboratories | |
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Si53019-A01A
19-OUTPUT PCIE GEN 3 BUFFER
Features
Nineteen 0.7 V current-mode, Spread spectrum tolerable
HCSL PCIe Gen 3 outputs
50 ps output-to-output skew
100 MHz /133 MHz PLL
operation, supports PCIe and
QPI
Fixed 0 ps input to output delay
Low phase jitter (Intel QPI, PCIe
Gen 1/Gen 2/Gen 3/Gen 4
PLL bandwidth SW SMBUS
common clock compliant
programming overrides the latch
value from HW pin
9 selectable SMBus addresses
Fixed external feedback path
Gen 3 SRNS Compliant
100 ps input-to-output delay
Extended Temperature:
–40 to 85 °C
8 dedicated OE pin
PLL or bypass mode
Package: 72-pin QFN
Ordering Information:
See page 32.
Applications
Server
Storage
Data Center
Network Security
Description
The Si53019-A01A is a 19-output, current mode HCSL differential clock
buffer that meets all of the performance requirements of the Intel
DB1900Z specification. The device is optimized for distributing reference
clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/
Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel
SMI) applications. The VCO of the device is optimized to support
100 MHz and 133 MHz operation. Each differential output can be enabled
through I2C for maximum flexibility and power savings. Measuring PCIe
clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool.
Download it for free at www.silabs.com/pcie-learningcenter.
Pin Assignments
VDDA
GNDA
IREF
100M_133M
HBW_BYPASS_LBW
PWRGD / PWRDN
GND
VDDR
CLK_IN
CLK_IN
SA_0
SDA
SCL
SA_1
FB_IN
FB_IN
FB_OUT
FB_OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Si53019-A01A
54 OE11
53 DIF_11
52 DIF_11
51 OE10
50 DIF_10
49 DIF_10
48 OE9
47 DIF_9
46 DIF_9
45 VDD
44 GND
43 OE8
42 DIF_8
41 DIF_8
40 OE7
39 DIF_7
38 DIF_7
37 OE6
Patents pending
Rev. 1.3 1/16
Copyright © 2016 by Silicon Laboratories
Si53019-A01A
1 page  
Si53019-A01A
Table 2. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)1
Parameter
Symbol
CLK 100 MHz, 133 MHz
Unit
Clock Stabilization Time2
Long Term Accuracy3,4,5
Absolute Host CLK Period (100 MHz)3,4,6
Absolute Host CLK Period (133 MHz)3,4,6
Slew Rate3,4,7
TSTAB
LACC
TABS
TABS
Edge_rate
Min
—
—
9.94900
7.44925
1.0
Typ Max
1.5 1.8
ms
— 100 ppm
— 10.05100
ns
7.55075
ns
3.0 4.0 V/ns
Slew Rate Matching3,8,10,11
Rise Time Variation3,8,9
TRISE_MAT/
TFALL_MAT
∆ Trise
—
—
7 20
— 125
%
ps
Fall Time Variation3,8,9
∆ Tfall
—
— 125
ps
Voltage High (typ 0.7 V)3,8,12
Voltage Low (typ 0.7 V)3,8,13
VHIGH
VLOW
660
–150
750
15
850
150
mV
mV
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8–2.0 V to the
time that stable clocks are output from the buffer chip (PLL locked).
3. Test configuration is Rs = 33.2 , Rp = 49.9, 2 pF for 100 transmission line; Rs = 27 , Rp = 42.2, 2 pF for 85
transmission line.
4. Measurement taken from differential waveform.
5. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are
99,750,00 Hz, 133,000,000 Hz.
6. The average period over any 1 µs period of time must be greater than the minimum and less than the maximum
specified period.
7. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from –150 mV
to +150 mV on the differential waveform. Scope is set to average because the scope sample clock is making most of
the dynamic wiggles along the clock edge Only valid for Rising CLOCK and Falling CLOCK. Signal must be monotonic
through the Vol to Voh region for Trise and Tfall.
8. Measurement taken from single-ended waveform.
9. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.
10. Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of clock verses the
falling edge rate (average) of CLOCK.
11. Rise/Fall matching is derived using the following, 2*(Trise - Tfall) / (Trise + Tfall).
12. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.
13. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.
14. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of
CLK.
15. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is
crossing.
16. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
17. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg – 0.700), Vcross(rel)
Max = 0.550 – 0.5 (0.700 – Vhavg), (see Figure 4–5 for further clarification).
18. Vcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK. This is the
maximum allowed variance in Vcross for any particular system.
19. Overshoot is defined as the absolute value of the maximum voltage.
20. Undershoot is defined as the absolute value of the minimum voltage.
Rev. 1.3
5
5 Page 
Si53019-A01A
Table 7. Phase Jitter (Continued)
Additive Phase Jitter
Bypass Mode
PCIe Gen 11,2,3
PCIe Gen 2 Low Band
F < 1.5 MHz1,3,4,5
— 4 — ps
— 0.08 —
ps
(RMS)
PCIe Gen 2 High Band
1.5 MHz < F < Nyquist1,3,4,5
— 1 — ps
(RMS)
PCIe Gen 3
(PLL BW 2–4 MHz, CDR = 10 MHz)1,3,4,5
PCIe Gen 4, Common Clock
(PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)1,4,5,8
Intel QPI & Intel® SMI
(4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)1,6,7
—
—
—
0.27
0.27
0.25
— ps
(RMS)
— ps
(RMS)
— ps
(RMS)
Intel QPI & Intel® SMI
(8 Gb/s, 100 MHz, 12 UI)1,6
Intel QPI & Intel® SMI
(9.6 Gb/s, 100 MHz, 12 UI)1,6
— 0.08 —
ps
(RMS)
— 0.07 —
ps
(RMS)
Notes:
1. Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a
smaller sample size have to be extrapolated to this BER target.
2. ζ = 0.54 implies a jitter peaking of 3 dB.
3. PCIe* Gen3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest
specification.
4. Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
5. Measured on 100 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
6. Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplied Clock Jitter Tool V1.6.3.
7. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be
extrapolated to this BER target.
8. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
9. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Rev. 1.3
11
11 Page | ||
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