PDF SI52143 Data sheet ( Hoja de datos )

Número de pieza	SI52143
Descripción	CLOCK GENERATOR
Fabricantes	Silicon Laboratories
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Si52143 PCI-EXPRESS GEN 1, GEN 2, & GEN 3 QUAD OUTPUT CLOCK GENERATOR WITH 25 MHZ REFERENCE CLOCK Features  PCI-Express Gen 1, Gen 2, Gen 3,  Four PCI-Express clocks and Gen 4 common clock compliant  25 MHz reference clock output  Gen 3 SRNS Compliant  25 MHz crystal input or clock input  Supports Serial ATA (SATA) at  Signal integrity tuning 100 MHz  I2C support with readback  Low power, push-pull HCSL capabilities compatible differential outputs  Triangular spread spectrum profile  No termination resistors required for maximum electromagnetic  Dedicated output enable hardware interference (EMI) reduction pins for each clock output  Spread enable pin on differential clocks  Industrial temperature –40 to 85 oC  3.3 V power supply  24-pin QFN package Applications  Network attached storage  Multi-function printer  Wireless access point  Routers Description The Si52143 is a spread-spectrum enabled PCIe clock generator that can source four PCIe clocks and a 25 MHz reference clock. The device has three hardware output enable pins for enabling the outputs (on the fly while powered on), and one hardware pin to control spread spectrum on PCIe clock outputs. In addition to the hardware control pins, I2C programmability is also available to dynamically control skew, edge rate and amplitude on the true, compliment, or both differential signals on the PCIe clock outputs. This control feature enables optimal signal integrity as well as optimal EMI signature on the PCIe clock outputs. Refer to AN636 for signal integrity tuning and configurability. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. Functional Block Diagram Ordering Information: See page 18 Pin Assignments VDD_REF 1 REF 2 SSON2 3 VSS_REF 4 OE_REF1 5 VDD_DIFF 6 24 23 22 21 20 19 18 OE[3:2]1 17 VDD_DIFF 25 GND 16 DIFF3 15 DIFF3 14 DIFF2 13 DIFF2 7 8 9 10 11 12 Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. Patents pending XIN/CLKIN XOUT SCLK SDATA OE_REF OE [1:0] OE [3:2] SSON PLL (SSC) Control & Memory Control RAM Divider REF DIFF0 DIFF1 DIFF2 DIFF3 Rev 1.3 12/15 Copyright © 2015 by Silicon Laboratories Si52143 1 page Si52143 Table 2. AC Electrical Specification Parameter Crystal Symbol Test Condition Min Long-term Accuracy Clock Input LACC Measured at VDD/2 differential — Duty Cycle CLKIN Rising and Falling Slew Rate Cycle to Cycle Jitter Long Term Jitter Input High Voltage Input Low Voltage Input High Current Input Low Current DIFF at 0.7 V TDC TR/TF TCCJ TLTJ VIH VIL IIH IIL Measured at VDD/2 Measured between 0.2 VDD and 0.8 VDD Measured at VDD/2 Measured at VDD/2 XIN/CLKIN pin XIN/CLKIN pin XIN/CLKIN pin, VIN = VDD XIN/CLKIN pin, 0 < VIN <0.8 45 0.5 — — 2 — — –35 Duty Cycle Output-to-Output Skew Cycle to Cycle Jitter PCIe Gen 1 Pk-Pk Jitter, Common Clock PCIe Gen 2 Phase Jitter, Common Clock TDC TSKEW TCCJ Pk-Pk RMSGEN2 Measured at 0 V differential Measured at 0 V differential Measured at 0 V differential PCIe Gen 1 10 kHz < F < 1.5 MHz 1.5 MHz< F < Nyquist Rate 45 — — 0 0 0 PCIe Gen 3 Phase Jitter, Common Clock RMSGEN3 PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz 0 PCIe Gen 3 Phase Jitter, Separate Reference No Spread, SRNS PCIe Gen 4 Phase Jitter, Common Clock RMSGEN3_SRNS PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz RMSGEN4 PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz — — Long Term Accuracy Rising/Falling Slew Rate LACC TR / TF Measured at 0 V differential Measured differentially from ±150 mV — 1 Voltage High VHIGH — Voltage Low VLOW –0.3 Crossing Point Voltage at 0.7 V Swing VOX 300 Notes: 1. Visit www.pcisig.com for complete PCIe specifications. 2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. Typ Max Unit — 250 ppm — 55 % — 4.0 V/ns — 250 ps — 350 ps — VDD+0.3 V — 0.8 V — 35 µA — — µA — 55 % — 50 ps 35 50 ps 40 50 ps 2 2.6 ps 2 2.6 ps 0.5 0.9 ps 0.35 0.64 ps 0.5 0.9 ps — 100 ppm — 8 V/ns — 1.15 V — —V — 550 mV Rev 1.3 5 5 Page Si52143 4. Control Registers 4.1. I2C Interface To enhance the flexibility and function of the clock synthesizer, an I2C interface is provided. Through the I2C Interface, various device functions are available, such as individual clock enablement. The registers associated with the I2C Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at system initialization, if any are required. Power management functions can only be programed in program mode and not in normal operation modes. 4.2. Data Protocol The clock driver I2C protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The block write and block read protocol is outlined in Table 5 while Table 6 outlines byte write and byte read protocol. The slave receiver address is 11010110 (D6h). Table 5. Block Read and Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 37 45:38 46 .... .... .... .... Block Write Protocol Description Start Slave address—7 bits Write Acknowledge from slave Command Code—8 bits Acknowledge from slave Byte Count—8 bits Acknowledge from slave Data byte 1—8 bits Acknowledge from slave Data byte 2—8 bits Acknowledge from slave Data Byte /Slave Acknowledges Data Byte N—8 bits Acknowledge from slave Stop Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 46:39 47 55:48 56 .... .... .... .... Block Read Protocol Description Start Slave address—7 bits Write Acknowledge from slave Command Code—8 bits Acknowledge from slave Repeat start Slave address—7 bits Read = 1 Acknowledge from slave Byte Count from slave—8 bits Acknowledge Data byte 1 from slave—8 bits Acknowledge Data byte 2 from slave—8 bits Acknowledge Data bytes from slave/Acknowledge Data Byte N from slave–8 bits NOT Acknowledge Stop Rev 1.3 11 11 Page

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