PDF SI52112-B6 Data sheet ( Hoja de datos )

Número de pieza	SI52112-B6
Descripción	PCI-EXPRESS GEN 3 DUAL OUTPUT CLOCK GENERATOR
Fabricantes	Silicon Laboratories
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No Preview Available ! Si52112-B5/B6 PCI-EXPRESS GEN 3 DUAL OUTPUT CLOCK GENERATOR Features  PCI-Express Gen 1, Gen 2,  Triangular spread spectrum Gen 3, and Gen 4 common clock profile for maximum EMI compliant reduction (Si52112-B6)  Gen 3 SRNS Compliant  Extended Temperature:  Low power HCSL differential –40 to 85 °C output buffers  3.3 V Power supply  Supports Serial-ATA (SATA) at  Small package 10-pin TDFN 100 MHz (3x3 mm)  No termination resistors required  Si52112-B5 does not support  25 MHz Crystal Input or Clock spread spectrum outputs input  Si52112-B6 supports 0.5% down spread outputs Applications  Network attached storage  Multi-function printer  Wireless access point  Routers Description Si52112-B5/B6 is a high-performance, PCIe clock generator that can source two PCIe clocks from a 25 MHz crystal or clock input. The clock outputs are compliant to PCIe Gen 1, Gen 2, Gen 3, Gen 3 SRNS and Gen 4 common clock specifications. The ultra-small footprint (3x3 mm) and industry leading low power consumption make Si52112-B5/B6 the ideal clock solution for consumer and embedded applications. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. Ordering Information: See page 13 Pin Assignments VDD 1 XOUT 2 XIN/CLKIN 3 VSS 4 VSS 5 10 VDD 9 DIFF2 8 DIFF2 7 DIFF1 6 DIFF1 Patents pending Functional Block Diagram VDD XIN/CLKIN XOUT PLL Divider DIFF1 DIFF2 VSS Rev 1.2 12/15 Copyright © 2015 by Silicon Laboratories Si52112-B5/B6 1 page Si52112-B5/B6 Table 3. AC Electrical Specifications Parameter Symbol Test Condition Min Crystal Long-term Accuracy Clock Input CLKIN Duty Cycle CLKIN Rise and Fall Times CLKIN Cycle-to-Cycle Jitter CLKIN Long Term Jitter Input High Voltage Input Low Voltage Input High Current Input Low Current DIFF Clocks Duty Cycle Skew Output Frequency Frequency Accuracy Slew Rate LACC TDC TR/TF TCCJ TLTJ VIH VIL IIH IIL TDC TSKEW FOUT FACC tr/f2 Measured at VDD/2 differential — Measured at VDD/2 Measured between 0.2 VDD and 0.8 VDD Measured at VDD/2 Measured at VDD/2 XIN/CLKIN pin XIN/CLKIN pin XIN/CLKIN pin, VIN = VDD XIN/CLKIN pin, 0 < VIN <0.8 45 0.5 — — 2 — — –35 Measured at 0 V differential Measured at 0 V differential VDD = 3.3 V All output clocks Measured differentially from ±150 mV 45 — — — 0.6 Cycle-to-Cycle Jitter PCIe Gen 1 Pk-Pk Jitter, Common Clock PCIe Gen 2 Phase Jitter, Common Clock PCIe Gen 3 Phase Jitter, Common Clock TCCJ Pk-PkGEN1 RMSGEN2 RMSGEN3 Measured at 0 V differential PCIe Gen 1 10 kHz < F < 1.5 MHz 1.5 MHz < F < Nyquist PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz — — — — — PCIe Gen 3 Phase Jitter, Separate Reference No Spread, SRNS PCIe Gen 4 Phase Jitter, Common Clock RMSGEN3_SRNS RMSGEN4 PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz — — Crossing Point Voltage at 0.7 V Swing Voltage High Voltage Low VOX VHIGH VLOW 300 — –0.3 Notes: 1. Visit www.pcisig.com for complete PCIe specifications. 2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5. 3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. Typ Max Unit — 250 ppm — 55 % — 4.0 V/ns — 250 ps — 350 ps — VDD+0.3 V — 0.8 V — 35 µA — — µA — 55 % — 60 ps 100 — MHz — 100 ppm — 4.0 V/ns 28 70 ps 24 86 ps 1.35 3.0 ps 1.4 3.1 ps 0.4 1.0 ps 0.28 0.71 ps 0.4 1.0 ps — 550 mV — 1.15 V — —V Rev 1.2 5 5 Page 4. Pin Descriptions 4.1. 10-Pin TDFN Si52112-B5/B6 VDD 1 XOUT 2 XIN/CLKIN 3 VSS 4 VSS 5 10 VDD 9 DIFF2 8 DIFF2 7 DIFF1 6 DIFF1 Pin # 1 2 3 4 5 6 7 8 9 10 Name VDD XOUT XIN/CLKIN VSS VSS DIFF1 DIFF1 DIFF2 DIFF2 VDD Figure 6. 10-Pin TDFN Table 7. 10-Pin TDFN Descriptions Type PWR 3.3 V power supply. Description O 25.00 MHz crystal output, Float XOUT if using only CLKIN (clock input). I 25.00 MHz crystal input or 3.3 V, 25 MHz clock Input. GND Ground. GND Ground. O, DIF 0.7 V, 100 MHz differential clock output. O, DIF 0.7 V, 100 MHz differential clock output. O, DIF 0.7 V, 100 MHz differential clock output. O, DIF 0.7 V, 100 MHz differential clock output. PWR 3.3 V power supply. Rev 1.2 11 11 Page

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