PDF SI52111-B6 Data sheet ( Hoja de datos )

Número de pieza	SI52111-B6
Descripción	PCI-EXPRESS GEN 3 SINGLE OUTPUT CLOCK GENERATOR
Fabricantes	Silicon Laboratories
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No Preview Available ! Si52111-B5/B6 PCI-EXPRESS GEN 3 SINGLE OUTPUT CLOCK GENERATOR Features  PCI-Express Gen 1, Gen 2,  Triangular spread spectrum Gen 3, and Gen 4 common clock profile for maximum EMI compliant reduction (Si52111-B6)  Gen 3 SRNS Compliant  Extended Temperature:  Low power HCSL differential –40 to 85 °C output buffer  3.3 V Power supply  Supports Serial-ATA (SATA) at  Small package 10-pin TDFN 100 MHz (3x3 mm)  No termination resistors required  Si52111-B5 does not support  25 MHz Crystal Input or Clock spread spectrum outputs input  Si52111-B6 supports 0.5% down spread outputs Applications  Network Attached Storage  Multi-function Printer  Wireless Access Point  Routers Description Si52111-B5/B6 is a high-performance, PCIe clock generator that can source one PCIe clock output from a 25 MHz crystal or clock input. The clock output is compliant to PCIe Gen 1, Gen 2, Gen 3, Gen 3 SRNS and Gen 4 common clock specifications. The ultra-small footprint (3x3 mm) and industry leading low power consumption make Si52111-B5/B6 the ideal clock solution for consumer and embedded applications. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. Ordering Information: See page 13 Pin Assignments VDD 1 XOUT 2 XIN/CLKIN 3 VSS 4 VSS 5 10 VDD 9 NC 8 NC 7 DIFF1 6 DIFF1 Functional Block Diagram Patents pending VDD XIN/CLKIN XOUT Rev 1.2 12/15 PLL Divider DIFF1 VSS Copyright © 2015 by Silicon Laboratories Si52111-B5/B6 1 page Si52111-B5/B6 Table 3. AC Electrical Specifications (Continued) Parameter Cycle-to-Cycle Jitter PCIe Gen 1 Pk-Pk Jitter, Common Clock PCIe Gen 2 Phase Jitter, Common Clock PCIe Gen 3 Phase Jitter, Common Clock Symbol TCCJ Pk-PkGEN1 RMSGEN2 RMSGEN3 Test Condition Measured at 0 V differential PCIe Gen 1 10 kHz < F < 1.5 MHz 1.5 MHz < F < Nyquist Includes PLL BW 2–4 MHz, CDR = 10 MHz PCIe Gen 3 Phase Jitter, Separate Reference No Spread, SRNS PCIe Gen 4 Phase Jitter, Common Clock RMSGEN3_SRNS RMSGEN4 PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz Crossing Point Voltage at 0.7 V Swing Voltage High Voltage Low Spread Range Modulation Frequency VOX VHIGH VLOW SRNG FMOD Down Spread, -B6 only -B6 only Enable/Disable and Set-up Clock Stabilization from Power-up Stopclock Set-up Time TSTABLE TSS Notes: 1. Visit www.pcisig.com for complete PCIe specifications. 2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5 3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter. Min — — — — — — — 300 — –0.3 — 30 — 10.0 Typ 28 24 1.35 1.4 0.4 0.28 0.4 — — — –0.5 31.5 — — Max Unit 70 ps 86 ps 3.0 ps 3.1 ps 1.0 ps 0.71 ps 1.0 ps 550 mV 1.15 — — 33 V V % kHz 3 ms — ns Rev 1.2 5 5 Page 4. Pin Descriptions 4.1. 10-Pin TDFN Si52111-B5/B6 Pin # 1 2 3 4 5 6 7 8 9 10 VDD 1 XOUT 2 XIN/CLKIN 3 VSS 4 VSS 5 10 VDD 9 NC 8 NC 7 DIFF1 6 DIFF1 Name VDD XOUT XIN/CLKIN VSS VSS DIFF1 DIFF1 NC NC VDD Figure 6. 10-Pin TDFN Table 7. 10-Pin TDFN Descriptions Type PWR 3.3 V Power supply. Description O 25.00 MHz crystal output, Float XOUT if using only CLKIN (clock input). I 25.00 MHz crystal input or 3.3 V, 25 MHz clock Input. GND Ground. GND Ground. O, DIF 0.7 V, 100 MHz differentials clock output. O, DIF 0.7 V, 100 MHz differentials clock output. NC No Connect. Do not connect this pin to anything. NC No Connect. Do not connect this pin to anything. PWR 3.3 V Power supply Rev 1.2 11 11 Page

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Número de pieza	Descripción	Fabricantes
SI52111-B5	PCI-EXPRESS GEN 3 SINGLE OUTPUT CLOCK GENERATOR	Silicon Laboratories
SI52111-B6	PCI-EXPRESS GEN 3 SINGLE OUTPUT CLOCK GENERATOR	Silicon Laboratories

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