PDF SI52111-A1 Data sheet ( Hoja de datos )

Número de pieza	SI52111-A1
Descripción	PCI-EXPRESS GEN 1 SINGLE OUTPUT CLOCK GENERATOR
Fabricantes	Silicon Laboratories
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No Preview Available ! Si52111-A1/A2 PCI-EXPRESS GEN 1 SINGLE OUTPUT CLOCK GENERATOR Features  PCI-Express Gen 1 compliant  3.3 V Power supply  Low power HCSL differential output buffer  Small package 10-pin TDFN (3x3 mm)  Supports Serial-ATA (SATA) at  Si52111-A1 does not support 100 MHz spread spectrum outputs  No termination resistors required  Si52111-A2 supports 0.5% down  25 MHz Crystal Input or Clock spread outputs input  For PCIe Gen 2 applications, see  Triangular spread spectrum Si52111-B3/B4 profile for maximum EMI  For PCIe Gen 3 applications, see reduction (Si52111-A2) Si52111-B5/B6  Extended Temperature: –40 to 85 °C Ordering Information: See page 13 Applications  Network Attached Storage  Multi-function Printer  Wireless Access Point  Routers Description Si52111-A1/A2 is a high-performance, PCIe clock generator that can source one PCIe clock output from a 25 MHz crystal or clock input. The clock output is compliant to PCIe Gen 1 specifications. The ultra-small footprint (3x3 mm) and industry leading low power consumption make Si52111-A1/A2 the ideal clock solution for consumer and embedded applications. VDD Pin Assignments VDD 1 XOUT 2 XIN/CLKIN 3 VSS 4 VSS 5 10 VDD 9 NC 8 NC 7 DIFF1 6 DIFF1 Patents pending XIN/CLKIN XOUT PLL Divider VSS DIFF1 Rev 1.2 7/14 Copyright © 2014 by Silicon Laboratories Si52111-A1/A2 1 page Si52111-A1/A2 Table 3. AC Electrical Specifications Parameter Symbol Test Condition Crystal Long-term Accuracy Clock Input LACC Measured at VDD/2 differential CLKIN Duty Cycle CLKIN Rise and Fall Times CLKIN Cycle-to-Cycle Jitter CLKIN Long Term Jitter Input High Voltage Input Low Voltage Input High Current Input Low Current DIFF Clocks TDC TR/TF TCCJ TLTJ VIH VIL IIH IIL Measured at VDD/2 Measured between 0.2 VDD and 0.8 VDD Measured at VDD/2 Measured at VDD/2 XIN/CLKIN pin XIN/CLKIN pin XIN/CLKIN pin, VIN = VDD XIN/CLKIN pin, 0 < VIN <0.8 Duty Cycle Skew TDC TSKEW Measured at 0 V differential Measured at 0 V differential Output Frequency Frequency Accuracy Slew Rate FOUT FACC tr/f2 VDD = 3.3 V All output clocks Measured differentially from ±150 mV Cycle-to-Cycle Jitter PCIe Gen 1 Pk-Pk Jitter Crossing Point Voltage at 0.7 V Swing TCCJ Pk-PkGEN1 VOX Measured at 0 V differential PCIe Gen 1 Voltage High Voltage Low Spread Range Modulation Frequency VHIGH VLOW SRNG FMOD Down Spread, -A2 only -A2 only Enable/Disable and Set-up Clock Stabilization from Power-up TSTABLE Stopclock Set-up Time TSS Note: Visit www.pcisig.com for complete PCIe specifications. Min — 45 0.5 — — 2 — — –35 45 — — — 0.6 — — 300 — –0.3 — 30 — 10.0 Typ Max Unit — 250 ppm — 55 % — 4.0 V/ns — 250 ps — 350 ps — VDD+0.3 V — 0.8 V — 35 uA — — uA — 55 % — 60 ps 100 — MHz — 100 ppm — 4.0 V/ns 28 24 — — — –0.5 31.5 70 ps 86 ps 550 mV 1.15 — — 33 V V % kHz — 3 ms — — ns Rev 1.2 5 5 Page 4. Pin Descriptions 4.1. 10-Pin TDFN Si52111-A1/A2 VDD 1 XOUT 2 XIN/CLKIN 3 VSS 4 VSS 5 10 VDD 9 NC 8 NC 7 DIFF1 6 DIFF1 Pin # 1 2 3 4 5 6 7 8 9 10 Name VDD XOUT XIN/CLKIN VSS VSS DIFF1 DIFF1 NC NC VDD Figure 6. 10-Pin TDFN Table 7. 10-Pin TDFN Descriptions Type PWR 3.3 V Power supply. Description O 25.00 MHz crystal output, Float XOUT if using only CLKIN (clock input). I 25.00 MHz crystal input or 3.3 V, 25 MHz clock Input. GND Ground. GND Ground. O, DIF 0.7 V, 100 MHz differentials clock output. O, DIF 0.7 V, 100 MHz differentials clock output. NC No Connect. Do not connect this pin to anything. NC No Connect. Do not connect this pin to anything. PWR 3.3 V Power supply. Rev 1.2 11 11 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
SI52111-A1	PCI-EXPRESS GEN 1 SINGLE OUTPUT CLOCK GENERATOR	Silicon Laboratories
SI52111-A2	PCI-EXPRESS GEN 1 SINGLE OUTPUT CLOCK GENERATOR	Silicon Laboratories

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