PDF SI51218 Data sheet ( Hoja de datos )

Número de pieza	SI51218
Descripción	THREE OUTPUTS FACTORY PROGRAMMABLE CLOCK GENERATOR
Fabricantes	Silicon Laboratories
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No Preview Available ! Si51218 THREE OUTPUTS FACTORY PROGRAMMABLE CLOCK GENERATOR Features  Generates up to 3 LVCMOS  Separate voltage supply pins clock outputs from 32.768 kHz to VDD = 2.5 to 3.3 V 200 MHz  Accepts crystal or reference clock input VDDO= 1.8 to 3.3 V (VDDO ≤ VDD)  Low cycle-cycle jitter  Programmable output rise and 3 to 166 MHz reference clock input fall times 8 to 48 MHz crystal input  Programmable FSEL, PD and OE input functions  Ultra small 8-pin TDFN package (1.4 mm x 1.6 mm)  Low power dissipation  Operation temperature: 0–70 C Applications  Crystal / XO replacement  Digital Media players  Portable Devices  DTV/IPTV Ordering Information: See page 10. Pin Assignments Description The factory programmable Si51218 is a low power, small footprint and frequency flexible programmable clock generator targeting low power, low cost and high volume consumer and embedded applications. The device operates from a single crystal or an external clock source and generates up to 3 clock outputs from 32.768 kHz to 200 MHz. They are factory programmed to provide customized output frequencies, control inputs and ac parameter tuning like output drive strength that are optimized for customer board condition and application requirements. A separate VDDO supply pin supports clock outputs at a different voltage level. VDD 1 XOUT 2 XIN/CLKIN 3 CLKOUT1/REFOUT1 4 FSEL/OE Si51218 8 VDDO 7 CLKOUT3 6 CLKOUT2/REFOUT2 FSEL/OE/PD# 5 VSS Patents pending Functional Block Diagram XIN/CLKIN 3 XOUT 2 VDDO 8 VDD 1 VSS 5 PLLwith ModulationControl To Pin 6/7 Clock Drivers Programmable ConfigurationRegister V-Reg ToCore ToPin4ClockDriver and Oscillator Buffers, Dividers and Switch Matrix 4 CLKOUT1/REFOUT1(VDD) OE/FSEL 6 CLKOUT2/REFOUT2(VDDO) OE/FSEL/PD# 7 CLKOUT3(VDDO) Rev. 1.0 3/14 Copyright © 2014 by Silicon Laboratories Si51218 1 page Si51218 Table 2. AC Electrical Specifications (VDD=3.3 V ± 10% or VDD=2.5 V ± 5%, TA=0 to 70 oC) Parameter Input Frequency Range Input Frequency Range Output Frequency Range Frequency Accuracy Output Duty Cycle Input Duty Cycle Output Rise Time Output Fall Time Period Jitter Period Jitter Cycle-to-Cycle Jitter Power-up Time Symbol FIN1 FIN2 FOUT FACC DCOUT DCIN tr tf PJ1 PJ2 CCJ tPU Test Condition Crystal input Reference clock Input Configuration dependent Measured at VDD/2 CLKIN, CLKOUT through PLL CLKOUT1/2/3 in MHz range CL=15 pF, 20 to 80% CLKOUT1/2/3 in MHz range CL=15 pF, 20 to 80% CLKOUT1/2/3 in MHz range, VDD=VDDO=3.3 V, CL=15 pF CLKOUT1/3 at 32.768KHz, VDD=VDDO=3.3 V, CL=15 pF CLKOUT1/2/3, in MHz range VDD=VDDO=3.3 V, CL=15 pF Time from 0.9 VDD to valid fre- quencies at all clock outputs Min 8 3 0.032768 — 45 30 — Typ — — — 0 50 50 1 —1 — 150* — 1500* — 100* — 1.2 Output Enable Time tOE Time from OE raising edge to — active at outputs (asynchronous) 15 Output Disable Time tOD Time from OE falling edge to — active at outputs (asynchronous) 15 *Note: Jitter performance depends on configuration and programming parameters. Max 48 166 200 — 55 70 3.0 3.0 — — — 5.0 — — Unit MHz MHz MHz ppm % % ns ns ps ps ps ms ns ns Rev. 1.0 5 5 Page 6. Package Outline: 8-pin TDFN Si51218 Figure 1. 8-Pin TDFN Package Table 7. Package Diagram Dimensions Dimension A Min 0.70 Nom 0.75 Max 0.80 A1 0.00 0.02 0.05 A3 0.20 REF. b 0.15 0.20 0.25 D 1.60 BSC D2 1.00 1.05 1.10 e 0.40 BSC E 1.40 BSC E2 0.20 0.25 0.30 L 0.30 0.35 0.40 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.07 eee 0.08 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 11 11 Page

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