PDF SI8901 Data sheet ( Hoja de datos )

Número de pieza	SI8901
Descripción	ISOLATED MONITORING ADC
Fabricantes	Silicon Laboratories
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No Preview Available ! Si8900/1/2 ISOLATED MONITORING ADC Features  ADC 3 input channels 10-bit resolution 2 µs conversion time  Isolated serial I/O port UART (Si8900) I2C/SMbus (Si8901) 2.5 MHz SPI port (Si8902)  Transient immunity: 45 kV/µs (typ) Applications  Temperature range: –40 to +85 °C  >60-year life at rated working voltage  CSA component notice 5A approval  IEC 60950, 61010, 60601  VDE/IEC 60747-5-2  UL1577 recognized Up to 5 kVrms for 1 minute  Isolated data acquisition  AC mains monitor  Solar inverters Description  Isolated temp/humidity sensing  Switch mode power systems  Telemetry The Si8900/1/2 series of isolated monitoring ADCs are useful as linear signal galvanic isolators, level shifters, and/or ground loop eliminators in many applications including power-delivery systems and solar inverters. These devices integrate a 10-bit SAR ADC subsystem, supervisory state machine and isolated UART (Si8900), I2C/SMbus port (Si8901), or SPI Port (Si8902) in a single package. Based on Silicon Labs’ proprietary CMOS isolation technology, ordering options include a choice of 2.5 or 5 kV isolation ratings. All products are safety certified by UL, CSA, and VDE. The Si8900/1/2 devices offer a typical common-mode transient immunity performance of 45 kV/µs for robust performance in noisy and high-voltage environments. Devices in this family are available in 16-pin SOIC wide-body packages. Safety Approval  UL 1577 recognized Upto5 kVrmsfor1minute  CSA component notice 5A approval IEC 60950, 61010, 60601  VDE certification conformity  IED 60747-5-2 (VDE 0884 Part 2) Ordering Information: See page 25. Pin Assignments VDDA VREF AIN0 AIN1 AIN2 NC RST GNDA Si8900 VDDB NC NC Rx Tx NC VDDB GNDB VDDA VREF AIN0 AIN1 AIN2 RST RSDA GNDA Si8901 VDDB NC NC SCL SDA NC VDDB GNDB VDDA RST NC VREF AIN0 AIN1 AIN2 GNDA Si8902 VDDB NC SDO SCLK SDI EN VDDB GNDB Rev. 1.1 10/12 Copyright © 2012 by Silicon Laboratories Si8900/1/2 1 page Si8900/1/2 Table 2. Electrical Specifications (Continued) Parameter Symbol Test Condition Min Reset and Undervoltage Lockout Power-on RESET Voltage Threshold High Power-on RESET Voltage Threshold Low VDDA Power-On Reset Ramp Time VRSTH VRSTL tRAMP Time from VDDA = 0 V to VDDA > VRST — 1.7 — Power-On Reset Delay Time Output Side UVLO Threshold tPOR UVLO tRAMP < 1 ms — Output side UVLO Hysteresis H — Digital Inputs Logic High Level Input Voltage Logic Low Level Input Voltage Logic Input Current Input Capacitance Digital Outputs VIH VIL IIN CIN VIN = 0 V or VDD 0.7 x VDDB — –10 — Logic High Level Output Voltage VOH Logic Low Level Output Voltage VOL Digital Output Series Impedance Serial Ports ROUT VDDB = 5 V, IOH = –4 mA VDDB = 3.3 V, IOH = –4 mA VDDB = 3.3 to 5 V, IOL = 4 mA VDDB–0.4 3.1 — — UART Bit Rate SMBus/I2C Bit Rate Slave Address = 1111000x 60 — SPI Port — Typ — — — 2.3 100 — — 15 4.8 — 0.2 85 — — — Max Unit 1.8 V —V 1 ms 0.3 ms —V — mV —V 0.6 V +10 µA — pF —V —V 0.4 V — 234 kbps 240 kbps 2.5 Mbps Rev. 1.1 5 5 Page Si8900/1/2 4. ADC Data Transmission Modes The master can access ADC read-only registers ADC_H and ADC_L using either Demand Mode or Burst Mode. In Demand Mode (MODE = 1), the master triggers individual A/D conversions “on-demand”. In Burst Mode (MODE = 0), the Si890x performs ADC conversions continuously. Master to Slave Slave to Master Master writes CNFG_0 Command Byte to Si8900 Rx CNFG_0 Command Byte MODE = 1 tCONV CNFG_0 Command Byte ADC_H ADC_L Master reads updated CNFG_0 and ADC Data From Si8900 (Tx output) B) Si8900 Demand Mode ADC Read Master to Slave Slave to Master Master writes Slave Address and CNFG_0 Command Byte to Si8901 SDA Slave Address CNFG_0 Command Byte MODE = 1 Slave Address tCONV CNFG_0 Command Byte ADC_H ADC_L Master reads Slave Address, updated CNFG_0 and ADC Data from Si8901 (SDA pin) C) Si8901 Demand Mode ADC Read Master to Slave Slave to Master Master writes CNFG_0 Command Byte to Si8902 SDI The master must wait 8µS (track‐and‐hold time) before reading ADC data packet. CNFG_0 Command Byte MODE = 1 tCONV CNFG_0 Command Byte ADC_H ADC_L Master reads updated CNFG_0 and ADC Data from Si8902 SDO D) Si8902 Demand Mode ADC Read Figure 5. ADC Demand Mode Operation Referring to Figure 5A, a Demand Mode ADC read is initiated when the master writes a Command Byte to the Si8900. (The Command Byte is a copy of the CNFG_0 register that has been properly configured by the master.) Upon receipt of the Command Byte, the Si8900 updates its CNFG_0 register and triggers the start of an ADC conversion, at which time the master may immediately begin reading ADC conversion data from the Si8900 UART. The ADC conversion data packet contains a copy of the Command Byte for verification and two-bytes of ADC conversion data. The Si8901 (Figure 5B) ADC read transaction is identical to that of the Si8900 with the exception of the added I2C/SMBus Slave Address byte (Si8901 Slave Address is 0xF0). The Si8902 Demand Mode ADC read transaction (Figure 5C) is the same as that of the Si8900, except the master must wait 8 µs after the transmission of the Command Byte before reading the Si8902 SPI port because byte transmission time is two times shorter versus the Si8900/01. Rev. 1.1 11 11 Page

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