PDF SI5380 Data sheet ( Hoja de datos )

Número de pieza	SI5380
Descripción	Clock Generator
Fabricantes	Silicon Laboratories
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No Preview Available ! Ultra-Low Phase Noise, 12-output JESD204B Clock Generator Si5380 Data Sheet The Si5380 is a high performance, integer-based (M/N) clock generator for small cell ap- plications which demand the highest level of integration and phase noise performance. Based on Silicon Laboratories’ 4th generation DSPLL technology, the Si5380 combines frequency synthesis and jitter attenuation in a highly integrated digital solution that elimi- nates the need for external VCXO and loop filter components. A low cost, fixed-frequen- cy crystal provides frequency stability for free-run and holdover modes. This all-digital solution provides superior performance that is highly immune to external board distur- bances such as power supply noise. Applications • JESD204B clock generation • Remote Radio Units (RRU), Remote Access Networks (RAN), picocells, small cells • Wireless base stations (3G, GSM, W-CDMA, 4G/LTE, LTE-A) • Remote Radio Head (RRH), wireless repeaters, wireless backhaul • Data conversion sampling clocks (ADC, DAC, DDC, DUC) KEY FEATURES • Digital frequency synthesis eliminates external VCXO and analog loop filter components • Supports JESD204B clocking: DCLK and SYSREF • Input frequency range: • Differential: 10 MHz – 750 MHz • LVCMOS: 10 MHz – 250 MHz • Output frequency range: • Differential: 480 kHz – 1.47456 GHz • LVCMOS: 480 kHz – 250 MHz IN_SEL IN0 IN1 IN2 IN3/ FB_IN ÷P0 ÷P1 ÷P2 ÷P3 I2C_SEL SDA/SDI A1/SDO SCLK A0/CSb I2C/ SPI NVM INTRb LOLb Status Monitor PDNb RSTb 54MHz XTAL XA XB Si5380 OSC ÷R0A OUT0A DSPLL ÷R0 OUT0 ÷R1 OUT1 ÷R2 OUT2 ÷N0 t0 ÷N1 t1 ÷N2 t2 ÷N3 t3 ÷N4 t4 ÷R3 OUT3 ÷R4 OUT4 ÷R5 OUT5 ÷R6 OUT6 ÷R7 OUT7 ÷R8 OUT8 ÷R9 OUT9 ÷R9A OUT9A SYNCb OEb silabs.com \| Smart. Connected. Energy-friendly. Rev. 0.96 1 page Si5380 Data Sheet Functional Description Fin (MHz)1 LTE Device Clock Frequencies Fout (MHz)2 Note: 1. The Si5380 locks to any one of the frequencies listed in the Fin column and generates LTE device clock frequencies. 2. R output dividers allow other frequencies to be generated. These are useful for applications like JESD204B SYSREF clocks. 3.1.2 Si5380 Configuration for JESD204B Clock Generation The Si5380 can be used as a high performance, fully integrated JEDEC JESD204B jitter cleaner while eliminating the need for discrete VCXO and loop filter components. The Si5380 supports JESD204B subclass 0 and subclass 1 clocking by providing both device clocks (DCLK) and system reference clocks (SYSREF). The 12 clock outputs can be independently configured as device clocks or SYSREF clocks to drive JESD204B converters, FPGAs, or other logic devices. The Si5380 will clock up to four JESD204B targets using four or more DCLKs and four SYSREF clocks with adjustable delay.Each DCLK is grouped with a SYSREF clock in this configuration.If SYS- REF clocking is implemented in external logic, then the Si5380 will clock up to 12 JESD204B targets.Not limited to JESD204B applica- tions, each of the 12 outputs is individually configurable as a high performance output for traditional clocking applications. An example of a JESD204B frequency configuration is shown in the figure below. In this case, the N dividers determine the device clock frequency and the R dividers provide the divided SYSREF clock which is used as the lower frequency frame clock. The N divider path also in- cludes a configurable delay path (∆t) for controlling deterministic latency. The example shows a configuration where all the device clocks are controlled by a single delay path (∆t0) while the SYSREF clocks each have their own independent delay paths (∆t1 – ∆t4), though other combinations are also possible. Delay is programmable in steps of 68 ps in the range of ±128 steps (±8.6 ns). See the 3.5.15 Output Skew Control (Δt0 - Δt4) section for details on skew control. The SYSREF clock is always periodic and can be controlled (on/off) without glitches by enabling or disabling its output through register writes. IN_SEL[1:0] IN0 IN0b IN1 IN1b IN2 IN2b IN3/FB_IN IN3b/FB_INb Si5380 ÷P0 ÷P1 DSPLL ÷P2 PD LPF ÷P3 ÷M ÷5 ÷N0 t0 ÷R0A ÷R0 ÷R5 ÷R6 ÷R7 ÷R8 ÷R9 ÷R9A ÷N1 t1 ÷N2 t2 ÷N3 t3 ÷N4 t4 ÷R1 ÷R2 ÷R3 ÷R4 VDDO0 OUT0A OUT0Ab OUT0 OUT0b VDDO5 OUT5 OUT5b VDDO6 OUT6 OUT6b VDDO7 OUT7 OUT7b VDDO8 OUT8 OUT8b Device Clocks OUT9 OUT9b OUT9A OUT9Ab VDDO9 VDDO1 OUT1 OUT1b VDDO2 OUT2 OUT2b VDDO3 OUT3 OUT3b VDDO4 OUT4 OUT4b SYSREF Clocks Figure 3.1. Example Divider Configuration for Generating JESD204B Subclass 1 Clocks silabs.com \| Smart. Connected. Energy-friendly. Rev. 0.96 \| 4 5 Page Si5380 Data Sheet Functional Description 3.3.6 Zero Delay Mode A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs. The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally as shown in the figure below. This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. Any one of the outputs can be fed back to the IN3/FB_IN pins, although using the output driver that achieves the short- est trace length will help to minimize the input-to-output delay. The OUT9A and IN3/FB_IN pins are recommended for the external feed- back connection. The FB_IN input pins must be terminated and ac-coupled when zero delay mode is used. A differential external feed- back path connection is necessary for best performance. The order of the OUT9A and FB_IN polarities is such that they may be routed on the device side of the PCB without requiring vias or needing to cross each other. IN0 IN0b IN1 IN1b IN2 IN2b IN3/FB_IN IN3b/FB_INb ÷P0 ÷P1 ÷P2 ÷P3 Si5380 DSPLL PD LPF ÷M ÷5 ÷N0 t0 ÷N1 t1 ÷N2 t2 ÷N3 t3 ÷N4 t4 ÷R0A ÷R0 ÷R2 ÷R8 ÷R9 ÷R9A VDDO0 OUT0A OUT0Ab OUT0 OUT0b VDDO2 OUT2 OUT2b VDDO8 OUT8 OUT8b OUT9 OUT9b OUT9A OUT9Ab VDDO9 External Feedback Path Figure 3.6. Si5380 Zero Delay Mode Set-up silabs.com \| Smart. Connected. Energy-friendly. Rev. 0.96 \| 10 11 Page

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