PDF SI5375 Data sheet ( Hoja de datos )

Número de pieza	SI5375
Descripción	4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Fabricantes	Silicon Laboratories
Logotipo
Hay una vista previa y un enlace de descarga de SI5375 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! Si5375 4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Features  Highly integrated, 4–PLL clock  Integrated loop filter with multiplier/jitter attenuator programmable bandwidth as low  Four independent DSPLLs as 60 Hz support any-frequency synthesis  Simultaneous free-run and and jitter attenuation synchronous operation  Four inputs/four outputs  Each DSPLL can generate any frequency from 2 kHz to 808 MHz from a 2 kHz to 710 MHz input  Automatic/manual hitless input clock switching  Selectable output clock signal format (LVPECL, LVDS, CML, CMOS)  Ultra-low jitter clock outputs:  LOL and interrupt alarm outputs 350 fs rms (12 kHz– 20 MHz)  I2C programmable and 410 fs rms (50 kHz–80 MHz) typical  Single 1.8 V ±5% or 2.5 V ±10% operation with high PSRR on-  Meets ITU-T G.8251 and chip voltage regulator Telcordia GR-253-CORE OC-192 jitter specifications  10x10 mm PBGA Applications  High density any-port, any- protocol, any-frequency line cards  ITU-T G.709 OTN custom FEC  10/40/100G  OC-48/192, STM-16/64 Description  1/2/4/8/10G Fibre Channel  GbE/10GbE Synchronous Ethernet  Carrier Ethernet, multi-service switches and routers  MSPP, ROADM, P-OTS, muxponders Ordering Information: See page 48. The Si5375 is a highly-integrated, 4-PLL, jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. Each of the DSPLL® clock multiplier engines accepts an input clock ranging from 2 kHz to 710 MHz and generates an output clock ranging from 2 kHz to 808 MHz. The device provides virtually any frequency translation combination across this operating range. For asynchronous, free-running clock generation applications, the Si5375’s reference oscillator can be used as a clock source for any of the four DSPLLs. The Si5375 input clock frequency and clock multiplication ratio are programmable through an I2C interface. The Si5375 is based on Silicon Laboratories' third-generation DSPLL® technology, which provides any-frequency synthesis and jitter attenuation in a highly-integrated PLL solution that eliminates the need for external VCXO and loop filter components. Each DSPLL loop bandwidth is digitally-programmable, providing jitter performance optimization at the application level. The device operates from a single 1.8 or 2.5 V supply with on-chip voltage regulators with excellent PSRR. The Si5375 is ideal for providing clock multiplication and jitter attenuation in high port count optical line cards requiring independent timing domains. Rev. 1.0 8/12 Copyright © 2012 by Silicon Laboratories Si5375 1 page Si5375 Table 2. DC Characteristics (VDD = 1.8 ± 5%, 2.5 ±10%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Supply Current1 LVPECL Format 622.08 MHz Out — 870 All CKOUTs Enabled 980 IDD CMOS Format 19.44 MHz Out — 780 880 All CKOUTs Enabled Disable Mode — 660 — CKINn Input Pins2 Input Common Mode Voltage (Input Thresh- old Voltage) Input Resistance VICM CKNRIN Single-Ended Input Voltage Swing (See Absolute Specs) VISE 1.8 V ± 5% 2.5 V ± 10% Single-ended fCKIN < 212.5 MHz See Figure 1. fCKIN > 212.5 MHz See Figure 1. 0.9 1 20 0.2 0.25 — — 40 — — 1.4 1.7 60 — — Differential Input Voltage Swing (See Absolute Specs) VID fCKIN < 212.5 MHz See Figure 1. fCKIN > 212.5 MHz See Figure 1. 0.2 0.25 — — — — Output Clocks (CKOUTn)3,4 Common Mode CKOVCM LVPECL 100  load line-to-line VDD – 1.42 — Differential Output Swing CKOVD LVPECL 100  load line-to-line 1.1 — Single Ended Output Swing CKOVSE LVPECL 100  load line-to-line 0.5 — Differential Output Voltage CKOVD CML 100  load line-to-line 350 425 Common Mode Output Voltage CKOVCM CML 100  load line-to-line — VDD–0.36 Notes: 1. Current draw is independent of supply voltage. 2. No under- or overshoot is allowed. 3. LVPECL outputs require nominal VDD = 2.5 V. 4. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz. VDD –1.25 1.9 0.93 500 — Unit mA mA mA V V k VPP VPP VPP VPP V VPP VPP mVPP V Rev. 1.0 5 5 Page Si5375 Table 5. Performance Specifications VDD = 1.8 V ±5% or 2.5 V ±10%, TA = –40 to 85 °C Parameter Symbol Test Condition Min Typ PLL Performance* Lock Time Output Clock Phase Change tLOCKMP tP_STEP Start of ICAL to of LOL After clock switch f3  128 kHz — 35 — 200 Closed Loop Jitter Peaking Jitter Tolerance JPK JTOL — Jitter Frequency Loop Band- width 5000/BW 0.05 — 1 kHz Offset — –106 Phase Noise fout = 622.08 MHz CKOPN 10 kHz Offset 100 kHz Offset — –114 — –116 1 MHz Offset — –132 Subharmonic Noise SPSUBH Phase Noise @ 100 kHz Offset — –88 Spurious Noise SPSPUR Max spur @ n x F3 (n  1, n x F3 < 100 MHz) — –70 Jitter Generation JGEN fIN = fOUT = 622.08 MHz, BW = 120 Hz LVPECL output 12 kHz–20 MHz — 350 50 kHz–80 MHz — 410 *Note: fin = fout = 622.08 MHz; BW = 120 Hz; LVDS. Max Unit 1200 ms — ps 0.1 dB — ns pk-pk — dBc/Hz — dBc/Hz — dBc/Hz — dBc/Hz — dBc — dBc 410 fs rms — fs rms Rev. 1.0 11 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet SI5375.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
SI5374	4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR	Silicon Laboratories
SI5375	4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR	Silicon Laboratories
SI5376	4-PLL ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR	Silicon Laboratories

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar