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PDF ML620Q503 Data sheet ( Hoja de datos )
| Número de pieza | ML620Q503 | |
| Descripción | Ultra Low Power 16-bit Microcontroller | |
| Fabricantes | LAPIS Semiconductor | |
| Logotipo |  |
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ML620Q503/Q504
Ultra Low Power 16-bit Microcontroller
FEDL620Q504-01
Issue Date: Mar. 13, 2015
GENERAL DESCRIPTION
This LSI family is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as
synchronous serial port, UART, I2C bus interface (master), supply voltage level detect circuit, RC oscillation
type A/D converter, and successive approximation type A/D converter are incorporated around 16-bit CPU
nX-U16/100.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe
line architecture parallel processing. The Flash ROM that is installed as program memory achieves low-voltage
low-power consumption operation (read operation) is most suitable for battery-driven applications. And, this LSI
has a data flash-memory fill area by a software which can be written in.
The on-chip debug function that is installed enables program debugging and programming.
FEATURES
• CPU
− 16-bit RISC CPU (CPU name: nX-U16/100)
− Instruction system: 16-bit instructions
− Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division,
bit manipulations, bit logic operations, jump, conditional jump, call return stack
manipulations, arithmetic shift, and so on
− Build-in On-Chip debug function
− Minimum instruction execution time
30.5 µs (@32.768 kHz system clock)
62.5ns (@16 MHz system clock)
• Built-in coprocessor for multiplication, division, and multiply-accumulate operations
− Signed or unsigned operation setting
− Multiplication: 16bit × 16bit (operation time 4 cycles)
− Division: 32bit / 16bit (operation time 8 cycles)
− Division: 32bit / 32bit (operation time 16 cycles)
− Multiply-accumulate (non-saturating): 16bit × 16bit + 32bit (operation time 4 cycles)
− Multiply-accumulate (saturating): 16bit × 16bit + 32bit (operation time 4 cycles)
• Internal memory
− Supports ISP function (re-writing the program memory area by software)
− Number of segments
Product name
Flash memory
Program area*
Data area
ML620Q503
32KB (16K × 16bit)
2KB (1K × 16bit)
ML620Q504
64KB (32K × 16bit)
2KB (1K × 16bit)
*: including 1KB of unusable test area
SRAM
2KB (1K × 16bit)
6KB (3K × 16bit)
• Interrupt controller (INTC)
− 1 non-maskable interrupt sources (Internal source: 1)
− 37 maskable interrupt sources (Internal sources: 29, External sources: 8)
− Software interrupt (SWI): maximum 64 sources
− External interrupts and comparator allow edge selection and sampling selection
− Priority level (4-level) can be set for each interrupt
• Time base counter (TBC)
− Low-speed time base counter ×1 channel
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1 page  
FEDL620Q504-01
ML620Q503/Q504
BLOCK DIAGRAM
Block Diagram of ML620Q503/Q504
VSS
VDD
VDDL
VDDX
RESET_N
TEST0
TEST1_N
XT0
XT1
OSC0
OSC1
LSCLKO
OUTCLK
LSCLKI
CLKIN
IN0
CS0
RS0
RT0
RCT0
RCM
IN1
CS1
RS1
RT1
VREF
AIN0 to AIN11
CMP0P
CMP0M
CMP1P
CMP1M
EPSW1~3
PSW
Timing
Controller
On-Chip
ICE
Power
CPU (nX-U16/100)
GREG
0~15
ELR1~3
LR
EA
ALU
SP
Instruction
Decoder
Instruction
Register
Data-bus
RAM
2K/6Kbyte
RESET &
TEST
INT
1
OSC
INT
1
Interrupt
Controller
INT
1
WDT
INT
3
TBC
INT
8 Timer
×8
RC-ADC
SA-ADC
INT
1
INT
1
VLS
LLD
Analog
Comparator
x2
INT
2
ECSR1~3
DSR/CSR
PC
BUS
Controller
co-processor
(muldiv)
Program
Memory
(Flash)
32K/64Kbyte
INT
2
SSIO x 1
SSIOF x 1
INT
3 UART x 1
UARTF x 1
INT
2
I2C x 2
INT
4
Function
Timer x 4
SCK0
SIN0
SOUT0
SCKF0
SINF0
SOUTF0
SSF0
RXD0
TXD0
RXDF0
TXDF0
SDA0
SCL0
SDA1
SCL1
TMOUT0-9
TMOUTA-F
TMCKI0-7
INT
1 MELODY
MD0
INT
8
GPIO
P00 to P05
PXT0 to PXT1
P10 to P11
P20 to P23
P30 to P37
P40 to P47
P50 to P57
Figure 1. Block Diagram of ML620Q503/Q504
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5 Page 
FEDL620Q504-01
ML620Q503/Q504
Pin name I/O
I2C bus interface
SDA0
I/O
SCL0
O
SDA1
I/O
SCL1
O
Description
I2C0 data input/output pin. This pin has an NMOS
open drain output. When using this pin as a
function of the I2C, externally connect a pull-up
resistor.
I2C0 clock output pin.
This pin has an NMOS open drain output. When
using this pin as a function of the I2C, externally
connect a pull-up resistor.
I2C1 data input/output pin. This pin has an NMOS
open drain output. When using this pin as a
function of the I2C, externally connect a pull-up
resistor.
I2C1 clock output pin. This pin has an NMOS open
drain output. When using this pin as a function of
the I2C, externally connect a pull-up resistor.
Synchronous serial
SCK0
I/O Synchronous serial(SSIO) clock input/output pin.
SIN0
I Synchronous serial(SSIO) data input pin.
SOUT0
O Synchronous serial(SSIO) data output pin.
SCKF0
SINF0
SOUTF0
SSF0
I/O Synchronous serial with FIFO(SSIOF) clock
input/output pin.
I Synchronous serial with FIFO(SSIOF) data input
pin.
O Synchronous serial with FIFO(SSIOF) data output
pin.
I/O Synchronous serial with FIFO(SSIOF) select
input/output pin.
FTM
TMOUT0-9
TMOUTA-F
O FTM output pin.
TMCKI0-7 I External clock input pin for FTM
RC oscillation type A/D converter
IN0 I Channel 0 oscillation input pin.
CS0 O Channel 0 reference capacitor connection pin.
RS0 O Reference resistor connection pin of Channel 0.
RT0
RCT0
RCM
O Resistor sensor connection pin of Channel 0 for
measurement.
O Resistor/capacitor sensor connection pin of
Channel 0 for measurement.
O RC oscillation monitor pin.
IN1 I Oscillation input pin of Channel 1.
CS1 O Reference capacitor connection pin of Channel 1.
RS1 O Reference resistor connection pin of Channel 1.
RT1 O Resistor sensor connection pin for measurement
of Channel 1.
LSI pin name Pin mode
P30,P40,P50
2nd
P31,P41,P51
2nd
P34,P44,P54
2nd
P35,P45,P55
2nd
P02,P32,P42,P52
P01,P31,P41,P51
P00,P30,P40,P50
P22,P36,P46,P56
P21,P35,P45,P55
P20,P34,P44,P54
P23,P37,P47,P57
3rd
3rd
3rd
3rd
3rd
3rd
3rd
P02,P03,P22,P23
P32,P33,P36,P37,
P42,P43,P46,P47
P52,P53,P56,P57
P42,P43,P46,P47,
P52,P53,P56,P57
4th
1st
P00 2nd
P01 2nd
P03 2nd
P04 2nd
P02 2nd
P05 2nd
P20 2nd
P21 2nd
P22 2nd
P23 2nd
Logic
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L
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ML620Q503.PDF ] | |
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