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PDF CS5111 Data sheet ( Hoja de datos )

Número de pieza CS5111
Descripción 1.4A Switching Regulator
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CS5111
1.4 A Switching Regulator
with 5.0 V, 100 mA Linear
Regulator with Watchdog,
RESET and ENABLE
The CS5111 is a dual output power supply integrated circuit. It
contains a 5.0 V ± 2%, 100 mA linear regulator, a watchdog timer, a
linear output voltage monitor to provide a Power On Reset (POR) and
a 1.4 A current mode PWM switching regulator.
The 5.0 V linear regulator is comprised of an error amplifier, reference,
and supervisory functions. It has low internal supply current consumption
and provides 1.2 V (typical) dropout voltage at maximum load current.
The watchdog timer circuitry monitors an input signal (WDI) from
the microprocessor. It responds to the falling edge of this watchdog
signal. If a correct watchdog signal is not received within the
externally programmable time, a reset signal is issued.
The externally programmable active reset circuit operates correctly
for an output voltage (VLIN) as low as 1.0 V. During power up, or if the
output voltage shifts below the regulation limit, RESET toggles low
and remains low for the duration of the delay after proper output
voltage regulation is restored. Additionally a reset pulse is issued if the
correct watchdog is not received within the programmed time. Reset
pulses continue until the correct watchdog signal is received. The reset
pulse width and frequency, as well as the Power On Reset delay, are set
by one external RC network.
The current mode PWM switching regulator is comprised of an
error amplifier with selectable feedback inputs, a current sense
amplifier, an adjustable oscillator, and a 1.4 A output power switch
with anti–saturation control. The switching regulator can be
configured in a variety of topologies.
The CS5111 is load dump capable and has protection circuitry
which includes overvoltage shutdown, current limit on the linear and
switcher outputs, and an overtemperature limiter.
Features
Linear Regulator
– 5.0 V ± 2% @ 100 mA
Switching Regulator
– 1.4 A Peak Internal Switch
– 120 kHz Maximum Switching Frequency
– 5.0 V to 26 V Operating Supply Range
Smart Functions
– Watchdog
– RESET
– ENABLE
Protection
– Overvoltage
– Overtemperature
– Current Limit
54 V Peak Transient Capability
Internally Fused Leads in SO–24L Package
© Semiconductor Components Industries, LLC, 2001
January, 2001 – Rev. 9
1
http://onsemi.com
24
1
SO–24L
DWF SUFFIX
CASE 751E
MARKING
DIAGRAM
24
CS5111
AWLYYWW
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PIN CONNECTIONS
1
VIN
NC
NC
VSW
GND
GND
GND
GND
VFB1
VFB2
SELECT
COMP
24
ENABLE
VREG
VLIN
IBIAS
GND
GND
GND
GND
RESET
CDelay
WDI
COSC
ORDERING INFORMATION
Device
Package
Shipping
CS5111YDWF24
SO–24L 31 Units/Rail
CS5111YDWFR24 SO–24L 1000 Tape & Reel
Publication Order Number:
CS5111/D

1 page




CS5111 pdf
CS5111
PIN FUNCTION DESCRIPTION (continued)
PACKAGE PIN #
SO–24L
PIN SYMBOL
21 IBIAS
22 VLIN
23 VREG
24 ENABLE
FUNCTION
A resistor connected to GND sets internal bias currents as well as the COSC and
CDelay charge currents.
Regulated 5.0 V output from the linear regulator section.
Input voltage to the linear regulator and the internal supply circuitry.
Logic level input to shut down the switching regulator.
TYPICAL PERFORMANCE CHARACTERISTICS
4.5 0
–10
4.0 –20
–30
3.5
0
20 40 60 80 100
ILIN (mA)
Figure 2. 5.0 V Regulator Bias Current vs. Load Current
–40
0
0.5 1.0 1.5
ISW (A)
2.0
Figure 3. Supply Current vs. Switch Current
1.4 180
1.2 160
140
1.0
120
0.8 100
0.6 80
60
0.4
40
0.2 20
0
0 0.5 1.0 1.5 2.0
ISW (A)
Figure 4. Switch Saturation Voltage
0
0 500 1000 1500 2000 2500 3000
COSC (pF)
Figure 5. Oscillator Frequency (kHz) vs.
COSC (pF), Assuming RBIAS = 64.9 kW
http://onsemi.com
5

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CS5111 arduino
CS5111
VIN
VOUT = 18 V, Select > 2.0 V
VOUT = 16 V, Select < 0.8 V
L = 33 µH
VIN ENABLE
NC VREG
NC VLIN
COUT
88 µF
(2)
VSW
GND
IBIAS
GND
R1
100 k
GND
GND
CS5111
GND
GND
R2
946
R3
7.5 k
GND
GND
VFB1
(1)
VFB2
RESET
CDelay
SELECT
WDI
CCOMP
0.33 µF
COMP
COSC
5.0 V
100 µF
ESR < 8.0
RBIAS
64.9 k
Microprocessor
COSC
390 pF
CDelay
0.1 µF
Figure 16. A Typical Application Diagram with External Components Configured
in a Boost Topology
http://onsemi.com
11

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