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PDF MT9J003 Data sheet ( Hoja de datos )
| Número de pieza | MT9J003 | |
| Descripción | 1/2.3-Inch 10Mp CMOS Digital Image Sensor | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Features
1/2.3-Inch 10 Mp CMOS Digital Image Sensor
MT9J003 Datasheet, Rev. E
For the latest datasheet, please visit www.onsemi.com
Features
• 1080p digital video mode
• Simple two-wire serial interface
• Auto black level calibration
• Support for external mechanical shutter
• Support for external LED or xenon flash
• High frame rate preview mode with arbitrary down-
size scaling from maximum resolution
• Programmable controls: gain, horizontal and vertical
blanking, auto black level offset correction, frame
size/rate, exposure, left–right and top–bottom image
reversal, window size, and panning
• Data interfaces: parallel or four-lane serial high-speed
pixel interface (HiSPi) differential signaling (sub-
LVDS)
• On-die phase-locked loop (PLL) oscillator
• Bayer pattern downsize scaler
• Integrated position-based color and lens shading
correction
• One-time programmable memory (OTPM) for storing
module information
Applications
• Digital video cameras
• Digital still cameras
General Description
The ON Semiconductor MT9J003 is a 1/2.3-inch CMOS
active-pixel digital imaging sensor with an active pixel
array of 3856H x 2764V including border pixels. It can
support 10 megapixel (3664H x 2748V) digital still
images and a 1080p (3840H x 2160V) digital video
mode. It incorporates sophisticated on-chip camera
functions such as windowing, mirroring, column and
row skip modes, and snapshot mode. It is programma-
ble through a simple two-wire serial interface and has
very low power consumption.
Table 1:
Key Performance Parameters
Parameter
Value
Optical format
1/2.3-inch (4:3)
Active imager size
6.440 mm (H) x 4.616 mm (V), 7.923 mm
diagonal (Entire sensor)
6.119 mm (H) x 4.589 mm (V), 7.649 mm
diagonal (Still mode)
6.413 mm (H) x 3.607 mm (V), 7.358 mm
diagonal (Video mode)
Active pixels
3856H x 2764V (Entire sensor)
3664H x 2748V (4:3, Still mode)
3840H x 2160V (16:9, Video mode)
Pixel size
1.67 x 1.67 m
Chief ray angle
0°, 13.4°
Color filter array
RGB Bayer pattern
Shutter type
Electronic rolling shutter (ERS) with
global reset release (GRR)
Input clock frequency
6–48 MHz
Maxi-
mum
data
rate
Parallel
HiSPi (4-lane)
80 Mp/s at 80 MHz PIXCLK
2.8 Gbps
Still mode, 4:3 Programmable up to 15 fps serial I/F,
(3664H x 2748V) 7.5 fps parallel I/F
Frame
rate
Preview mode 30 fps with binning
VGA 60 fps with skip2bin2
1080p mode
60 fps using HiSPi I/F
(1920H x 1080V) 30 fps using parallel I/F
ADC resolution
12-bit, on-die
Responsivity
0.31 V/lux-sec (550nm)
Dynamic range
65.2 dB
SNRMAX
I/O Digital
34 dB
1.7–1.9 V (1.8 V nominal)
or 2.4–3.1 V (2.8 V nominal)
Supply Digital
voltage Analog
1.7–1.9 V (1.8 V nominal)
2.4–3.1 V (2.8 V nominal)
SLVS I/O
0.4 - 0.8 V (0.4 or 0.8 V nominal)
Power
Con-
sump-
tion
Still mode at 15
fps w/ serial I/F
638mW
Still mode at 7.5
fps w/ parallel I/F
388mW
Preview
250mW low power VGA
Standby
500W (typical, EXTCLK disabled)
Package
48-pin iLCC (10mm x 10mm) Bare die,
48pin Tiny PLCC (12mm x 12mm)
Operating temperature –30°C to +70°C (at junction)
MT9J003-DS Rev. E 5/15 EN
1 ©Semiconductor Components Industries, LLC,2015
1 page  
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
List of Tables
List of Tables
Table 1:
Table 2:
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Table 36:
Table 37:
Table 38:
Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Row Timing with HiSPi Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Row Timing with Parallel Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Row Timing with Parallel Interface Using Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Register Settings for Common Resolutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Definitions for Programming Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Output Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Configuration of the Pixel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
RESET_BAR and PLL in System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Signal State During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Streaming/STANDBY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Trigger Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Subsampling Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Minimum Row Time and Blanking Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Minimum Frame Time and Blanking Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Fine_Integration_Time Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Fine_Correction Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Recommended Gain Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
HiSPi Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
CRA (13.4°) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
DC Electrical Definitions and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Parallel Interface Configured to Use Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Two-Wire Serial Register Interface Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Two-Wire Serial Register Interface Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
I/O Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
HiSPi Rise and Fall Times at 480 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
HiSPi Rise and Fall Times at 360 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Channel, PHY and intra-PHY Skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Clock DLL Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Data DLL Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
48-Pin tPLCC Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
MT9J003-DS Rev. E 5/15 EN
5 ©Semiconductor Components Industries, LLC,2015.
5 Page 
MT9J003: 1/2.3-Inch 10 Mp CMOS Digital Image Sensor
Signal Descriptions
Signal Descriptions
Table 1 provides signal descriptions for MT9J003 die. For pad location and aperture
information, refer to the MT9J003 die data sheet.
Table 1:
Signal Descriptions
Pad Name
EXTCLK
RESET_BAR
(XSHUTDOWN)
SCLK
GPI[3:0]
TEST
SDATA
LINE_VALID
FRAME_VALID
DOUT[11:0]
PIXCLK
FLASH
SHUTTER
VPP
VDD_TX0
VDD_SLVS
VDD_SLVS_TX
VAA
VAA_PIX
AGND
VDD
VDD_IO
DGND
VDD_PLL
GND_PLL
PIXGND
SLVS_0P
SLVS_0N
SLVS_1P
SLVS_1N
SLVS_2P
SLVS_2N
Pad Type Description
Input Master clock input, 6–48 MHz.
Input Asynchronous active LOW reset. When asserted, data output stops and all internal registers are
restored to their factory default settings.
Input Serial clock for access to control and status registers.
Input
General purpose inputs. After reset, these pads are powered-down by default; this means that it is
not necessary to bond to these pads. Any of these pads can be configured to provide hardware
control of the standby, output enable, SADDR select, and shutter trigger functions.
Can be left floating if not used.
Input
Enable manufacturing test modes. It should not be left floating. It can be tied to ground or VDD_IO
when used in parallel or HiSPi. It should be connected to DGND for normal operation of the CCP2
configured sensor, or connected to VDD_IO power for the MIPI®-configured sensor.
I/O Serial data from READs and WRITEs to control and status registers.
Output LINE_VALID (LV) output. Qualified by PIXCLK.
Output FRAME_VALID (FV) output. Qualified by PIXCLK.
Output Parallel pixel data output. Qualified by PIXCLK.
Output Pixel clock. Used to qualify the LV, FV, and DOUT[11:0] outputs.
Output Flash output. Synchronization pulse for external light source. Can be left floating if not used.
Output Control for external mechanical shutter. Can be left floating if not used.
Supply Power supply used to program one-time programmable (OTP) memory. Disconnect pad when not
programming or when feature is not used.
Supply
PHY power supply. Digital power supply for the MIPI or CCP2 serial data interface. ON
Semiconductor recommends that VDD_TX0 is always tied to VDD when using an unpackaged
sensor.
Supply HiSPi power supply for data and clock output. This should be tied to VDD
Supply Digital power supply for the HiSPi I/O.
Supply Analog power supply.
Supply Analog power supply for the pixel array.
Supply Analog ground.
Supply Digital power supply.
Supply I/O power supply.
Supply Common ground for digital and I/O.
Supply PLL power supply.
Supply PLL ground.
Supply Pixel ground.
Output Lane 1 differential HiSPi (LVDS) serial data (positive). Qualified by the SLVS serial clock.
Output Lane 1 differential HiSPi (LVDS) serial data (negative). Qualified by the SLVS serial clock.
Output Lane 2 differential HiSPi (LVDS) serial data (positive). Qualified by the SLVS serial clock.
Output Lane 2 differential HiSPi (LVDS) serial data (negative). Qualified by the SLVS serial clock.
Output Lane 3 differential HiSPi (LVDS) serial data (positive). Qualified by the SLVS serial clock.
Output Lane 3 differential HiSPi (LVDS) serial data (negative). Qualified by the SLVS serial clock.
MT9J003-DS Rev. E 5/15 EN
11
©Semiconductor Components Industries, LLC,2015.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT9J003.PDF ] | |
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