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PDF MT9F002 Data sheet ( Hoja de datos )
| Número de pieza | MT9F002 | |
| Descripción | 1/2.3-Inch 14Mp CMOS Digital Image Sensor | |
| Fabricantes | ON Semiconductor | |
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MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor
Features
1/2.3-Inch 14 Mp CMOS Digital Image Sensor
MT9F002 Data Sheet, Rev. 9
For the latest data sheet, please visit: www.onsemi.com
Features
• 1.4 m pixel with ON Semiconductor A-Pix™
technology
• Simple two-wire serial interface
• Auto black level calibration
• Full HD support at 60 fps for maximum video
performance
• 20 percent extra image array area in full HD to
enable electronic image stabilization (EIS).
• Support for external mechanical shutter
• Support for external LED or xenon flash
• High frame rate preview mode with arbitrary down-
size scaling from maximum resolution
• Programmable controls: gain, horizontal and vertical
blanking, frame size/rate, exposure, left–right and
top–bottom image reversal, window size, and
panning
• Data interfaces: parallel or four-lane serial high-
speed pixel interface (HiSPi™) differential signaling
(SLVS)
• On-chip phase-locked loop (PLL) oscillator
• Bayer pattern downsize scaler
Applications
• Digital video cameras
• Digital still cameras
General Description
The ON Semiconductor MT9F002 is a 1/2.3-inch
CMOS active-pixel digital imaging sensor with an
active pixel array of 4608H x 3288V (4640H x 3320V
including border pixels). It can support 14-megapixel
(4384H x 3288V) digital still images and a 1080p plus
additional 20 percent pixels for electronic image stabi-
lization (4608H x 2592V) in digital video mode. The
MT9F002 sensor is programmable through a simple
two-wire serial interface, and has low power consump-
tion.
Table 1:
Key Performance Parameters
Parameter
Value
Optical format
Active pixels and imager size
Pixel size
Chief ray angle
Color filter array
Shutter type
Input clock frequency
Maxi-
mum
data
rate
Parallel
HiSPi (4-lane)
14M resolution
(4384H x 3288V)
Frame
rate
Preview VGA mode
1080p mode:
ADC resolution
Responsivity
Dynamic range
SNRMAX
I/O Digital
Digital
Supply
voltage
Analog
HiSPi PHY
HiSPi I/O (SLVS)
HiSPi I/O (HiVCM)
Power
Con-
sump-
tion
Full resolution 13.65
fps (HiSPi serial I/F,
12-bit)
1080p60 (HiSPi serial
I/F, 10-bit)
1080p30 (HiSPi serial
I/F, 10-bit)
Package
Operating temperature
1/2.3-inch (4:3)
• 4608H x 3288V: (entire array): 6.451mm (H)
x 4.603mm (V), 7.925mm diagonal
• 4384H x 3288V (4:3, still mode): 6.138mm
(H) x 4.603mm (V), 7.672mm diagonal
• 4608H x 2592V (16:9, video mode):
6.451mm (H) x 3.629mm (V), 7.402mm diagonal
1.4 m x 1.4m
0°, 11.4°, and 25°
RGB Bayer pattern
Electronic rolling shutter (ERS) with global reset
release (GRR)
2–64 MHz
96 Mp/s at 96 MHz PIXCLK
700 Mbps/lane
Programmable up to 13.7 fps for HiSPi I/F, 6.3 fps
for parallel I/F
• 30 fps with binning
• 60 fps with skip2bin2
• 60 fps using HiSPi interface
2304H x 1296V (1080p +20%EIS)
• 30 fps using parallel interface
2256H x 1268V (1080p +17%EIS)
12-bit, on-chip
0.724 V/lux-sec (550nm)
65.3 dB
35.5 dB
1.7–1.9 V (1.8 V nominal)
or 2.4–3.1 V (2.8 V nominal)
1.7–1.9 V (1.8 V nominal)
2.7–3.1 V (2.8 V nominal)
1.7–1.9 V (1.8 V nominal)
0.3 - 0.9 V (0.4 or 0.8 V nominal)
1.7–1.9 V (1.8 V nominal)
724 mW
XYbin2: 596 mW
XYbin2: 443 mW
48-pin iLCC (10 mm x 10 mm) and bare die
–30°C to +70°C (at junction)
MT9F002/D Rev. 9, 1/16 EN
1 ©Semiconductor Components Industries, LLC 2016,
1 page  
MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor
Functional Overview
Figure 2:
The image black level is calibrated to compensate for analog offset and ensure that the
ADC range is utilized well. It also reduces row noise in the image. The black level in the
output image involves Fine Digital Correction and addition of Data Pedestal (42 LSB for
10-bit ADC, 168 LSB for 12-bit ADC)
Data Flow Diagram
Analog Gain
Pixel
Output
Analog
ADC
DAC
Black Level
Calibration
Lens Shading Data
Correction Pedestal
12-bit
Analog
Offset
Calibration
Digital
Gain
Digital
Pixel Array
The sensor contains a set of control and status registers that can be used to control many
aspects of the sensor behavior including the frame size, exposure, and gain setting.
These registers can be accessed through a two-wire serial interface.
The output from the sensor is a Bayer pattern; alternate rows are a sequence of either
green and red pixels or blue and green pixels. The offset and gain stages of the analog
signal chain provide per-color control of the pixel data.
The control registers, timing and control, and digital processing functions shown in
Figure 1 on page 4 are partitioned into three logical parts:
• A sensor core that provides array control and data path corrections. The output of the
sensor core is a 12-bit parallel pixel data stream qualified by an output data clock
(PIXCLK), together with LINE_VALID (LV) and FRAME_VALID (FV) signals or a 4-lane
serial high-speed pixel interface (HiSPi).
• A digital shading correction block to compensate for color/brightness shading intro-
duced by the lens or chief ray angle (CRA) curve mismatch.
• Additional functionality is provided. This includes a horizontal and vertical image
scaler, a limiter, an output FIFO, and a serializer.
The output FIFO is present to prevent data bursts by keeping the data rate continuous.
Programmable slew rates are also available to reduce the effect of electromagnetic inter-
ference from the output interface.
A flash output signal is provided to allow an external xenon or LED light source to
synchronize with the sensor exposure time. Additional I/O signals support the provision
of an external mechanical shutter.
The sensor core uses a Bayer color pattern, as shown in Figure 3. The even-numbered
rows contain green and red pixels; odd-numbered rows contain blue and green pixels.
Even-numbered columns contain green and blue pixels; odd-numbered columns
contain red and green pixels.
MT9F002/D Rev. 9, 1/16 EN
5 ©Semiconductor Components Industries, LLC,2016.
5 Page 
MT9F002: 1/2.3-Inch 14 Mp CMOS Digital Image Sensor
Signal Descriptions
Table 3: Signal Descriptions (continued)
Signal
SLVS_3N
Type
Output
SLVS_CP
Output
SLVS_CN
Output
LINE_VALID
FRAME_VALID
DOUT[11:0]
PIXCLK
FLASH
Output
Output
Output
Output
Output
SHUTTER
Output
Description
Lane 4 differential HiSPi (SLVS) serial data (negative). Qualified by the SLVS
serial clock.
Differential HiSPi (SLVS) serial clock (positive). Qualified by the SLVS serial
clock.
Differential HiSPi (SLVS) serial clock (negative). Qualified by the SLVS serial
clock.
LINE_VALID (LV) output. Qualified by PIXCLK.
FRAME_VALID (FV) output. Qualified by PIXCLK.
Parallel pixel data output. Qualified by PIXCLK.
Pixel clock. Used to qualify the LV, FV, and DOUT[11:0] outputs.
Flash output. Synchronization pulse for external light source. Can be left
floating if not used.
Control for external mechanical shutter. Can be left floating if not used.
Figure 7: 48-Pin iLCC HiSPi Package Pinout Diagram
VDD_HiSPi
VDD_IO
DGND
VDD
EXTCLK
VDD
DGND
VDD_IO
SDATA
SCLK
TEST
RESET_BAR
6 5 4 3 2 1 48 47 46 45 44 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 20 21 22 23 24 25 26 27 28 29 30
AGND
VAA
NC
NC
VAA
AGND
VAA_PIX
VAA_PIX
NC
NC
VAA
AGND
MT9F002/D Rev. 9, 1/16 EN
11
©Semiconductor Components Industries, LLC,2016.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT9F002.PDF ] | |
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