PDF AS4C64M16D2 Data sheet ( Hoja de datos )

Número de pieza	AS4C64M16D2
Descripción	1Gb (64M x 16 bit) DDRII Synchronous DRAM (SDRAM)
Fabricantes	Alliance Semiconductor
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AS4C64M16D2 1Gb (64M x 16 bit) DDRII Synchronous DRAM (SDRAM) Alliance Memory Confidential Advanced (Rev. 1.0 April 2012) Features • JEDEC Standard Compliant • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Power supplies: VDD & VDDQ = +1.8V ± 0.1V • Operating temperature: - Commercial (0 ~ 85°C) - Industrial (-40 ~ 95°C) • Supports JEDEC clock jitter specification • Fully synchronous operation • Fast clock rate: 400MHz • Differential Clock, CK & CK# • Bidirectional single/differential data strobe -DQS & DQS# • 8 internal banks for concurrent operation • 4-bit prefetch architecture • Internal pipeline architecture • Precharge & active power down • Programmable Mode & Extended Mode registers • Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5, 6 • WRITE latency = READ latency - 1 tCK • Burst lengths: 4 or 8 • Burst type: Sequential / Interleave • DLL enable/disable • On-die termination (ODT) • RoHS compliant • Auto Refresh and Self Refresh • 8192 refresh cycles / 64ms -Average refresh period 7.8µs @ 0℃≦TC≦+85℃ 3.9µs @ +85℃＜TC≦+95℃ • 84-ball 8 x 12.5 x 1.2mm (max) FBGA package - Pb and Halogen Free Overview The AS4C64M16D2 is a high-speed CMOS Double- Data- Rate-Two (DDR2), synchronous dynamic random - access memory (SDRAM) containing 1024 Mbits in a 16- bit wide data I/Os. It is internally configured as a 8- bank DRAM, 8 banks x 8Mb addresses x 16 I/Os. The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, Write latency = Read latency -1 and On Die Termination(ODT). All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling) All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in RAS #, CAS# multiplexing style. Accesses begin with the registration of a Bank Activate command, and then it is followed by a Read or Write command. Read and write accesses to the DDR2 SDRAM are 4 or 8-bit burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Operating the eight memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. An auto precharge function may be enabled to provide a self- timed row precharge that is initiated at the end of the burst sequence. A sequential and gapless data rate is possible depending on burst length, CAS latency, and speed grade of the device. Table 1. Ordering Information Part Number Clock Frequency Data Rate AS4C64M16D2-25BCN 400MHz 800Mbps/pin AS4C64M16D2-25BIN 400MHz 800Mbps/pin B: indicates 84-ball (8.0 x 12.5 x 1.2mm) FBGA package C: indicates commercial temperature I: indicates industrial temperature N: indicates Pb and Halogen Free ROHS Power Supply VDD 1.8V, VDDQ 1.8V VDD 1.8V, VDDQ 1.8V Package FBGA FBGA Table 2. Speed Grade Information Speed Grade Clock Frequency DDR2-800 400 MHz CAS Latency 5 tRCD (ns) 12.5 tRP (ns) 12.5 Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. 1 Rev. 1.1 April. /2012 1 page AS4C64M16D2 Table 1. Ball Descriptions Symbol Type Description CK, CK# Input Differential Clock: CK, CK# are driven by the system clock. All SDRAM input signals are sampled on the crossing of positive edge of CK and negative edge of CK#. Output (Read) data is referenced to the crossings of CK and CK# (both directions of crossing). CKE BA0-BA2 A0-A12 Input Input Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes LOW synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains LOW. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. Bank Address: BA0-BA2 define to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. Address Inputs: A0-A12 are sampled during the BankActivate command (row address A0- A12) and Read/Write command (column address A0-A9 with A10 defining Auto Precharge). CS# RAS# CAS# WE# LDQS, LDQS# UDQS UDQS# LDM, UDM DQ0 - DQ15 Input Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code. Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the crossing of positive edges of CK and negative edge of CK#. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the BankActivate command is selected and the bank designated by BA is turned on to the active state. When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by BA is switched to the idle state after the precharge operation. Input Input Input / Output Column Address Strobe: The CAS# signal defines the operation commands in conjunction with the RAS# and WE# signals and is latched at the crossing of positive edges of CK and negative edge of CK#. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS# "LOW." Then, the Read or Write command is selected by asserting WE# “HIGH " or “LOW". Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the crossing of positive edges of CK and negative edge of CK#. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM. LDQS is for DQ0~7, UDQS is for DQ8~15. The data strobes LDOS and UDQS may be used in single ended mode or paired with LDQS# and UDQS# to provide differential pair signaling to the system during both reads and writes.A control bit at EMR (1)[A10] enables or disables all complementary data strobe signals. Input Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle. LDM masks DQ0-DQ7, UDM masks DQ8-DQ15. Input / Data I/O: The Data bus input and output data are synchronized with positive and Output negative edges of DQS/DQS#. The I/Os are byte-maskable during Writes. Alliance Memory Inc. reserves the right to change products or specification without notice. 5 Rev. 1.1 April. /2012 5 Page AS4C64M16D2 Table 4. Extended Mode Register EMR (1) Bitmap BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field 03 0 1 Qoff 03 DQS# OCD program Rtt Additive Latency Rtt D.I.C DLL Extended Mode Register BA1 BA0 MRS mode 00 MR 0 1 EMR(1) 1 0 EMR(2) 1 1 EMR(3) A6 A2 00 01 10 11 Rtt(NOMINAL) ODT Disable 75Ω 150Ω 50Ω A0 DLL Enable 0 Enable 1 Disable A9 A8 A7 OCD Calibration Program 0 0 0 OCD Calibration mode exit; maintain setting Output Driver A1 Impedance Control 0 0 1 Reserved 0 Full strength 0 1 0 Reserved 1 Reduced strength 1 0 0 Reserved 1 1 1 OCD Calibration default1 A5 A4 A3 Additive Latency A12 Qoff 2 000 001 0 1 0 Output buffer enabled 010 2 A10 DQS# 1 Output buffer disabled 011 3 0 Enable 100 4 1 Disable 101 5 110 Reserved 111 Reserved NOTE 1: After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000. NOTE 2: Output disabled – DQs, DQSs, DQSs#.This feature is intended to be used during IDD characterization of read current. NOTE 3: A11 and BA2 are reserved for future use and must be set to 0 when programming the MR. Alliance Memory Inc. reserves the right to change products or specification without notice. 11 Rev. 1.1 April. /2012 11 Page

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