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PDF ASM3P622S00E Data sheet ( Hoja de datos )
| Número de pieza | ASM3P622S00E | |
| Descripción | Low Frequency Peak EMI Reduction IC | |
| Fabricantes | ON Semiconductor | |
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ASM3P622S00B,
ASM3P622S00E
Product Preview
Low Frequency
TIMING SAFEt Peak EMI
Reduction IC
Description
ASM3P622S00B/E is a versatile, 3.3 V Zero−delay buffer designed
to distribute low frequency Timing−Safe clocks with Peak EMI
reduction. ASM3P622S00B is an eight−pin version, accepts one
reference input and drives out one low−skew Timing−Safe clock.
ASM3P622S00E accepts one reference input and drives out eight
low−skew Timing−Safe clocks.
ASM3P622S00B/E has an SS% that selects 2 different Deviation
and associated Input−Output Skew (TSKEW). Refer to Spread
Spectrum Control and Input−Output Skew table for details.
ASM3P622S00E has a CLKOUT for adjusting the Input−Output
clock delay, depending upon the value of capacitor connected at this
pin to GND.
ASM3P622S00B/E operates from a 3.3 V supply and is available in
two different packages, as shown in the ordering information table,
over commercial and Industrial temperature range.
Application
ASM3P622S00B/E is targeted for use in Displays and memory
interface systems.
Features
• Low Frequency Clock Distribution with Timing−Safe Peak EMI
Reduction
• Input Frequency Range: 4 MHz − 20 MHz
• 2 Different Spread Selection Options
• Spread Spectrum can be Turned ON/OFF
• External Input−Output Delay Control Option
• Supply Voltage: 3.3 V ± 0.3 V
• Commercial and Industrial Temperature Range
• Packaging Information:
ASM3P622S00B: 8 pin SOIC, and TSSOP
ASM3P622S00E: 16 pin SOIC, and TSSOP
• The First True Drop−in Solution
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
http://onsemi.com
TSSOP−8
T SUFFIX
CASE 948AL
SOIC−8
S SUFFIX
CASE 751BD
TSSOP−16
T SUFFIX
CASE 948AN
SOIC−16
S SUFFIX
CASE 751BG
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. P2
1
Publication Order Number:
ASM3P622S00/D
1 page  
ASM3P622S00B, ASM3P622S00E
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rating
Unit
VDD
Supply Voltage to Ground Potential
−0.5 to +4.6
V
VIN DC Input Voltage (CLKIN)
−0.5 to +7
V
TSTG
Storage temperature
−65 to +125
°C
Ts Max. Soldering Temperature (10 sec)
260 °C
TJ Junction Temperature
150 °C
TDV Static Discharge Voltage (As per JEDEC STD22− A114−B)
2 KV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. OPERATING CONDITIONS
Parameter
Description
Min Max Unit
VDD
Supply Voltage
3.0 3.6 V
TA Operating Temperature (Ambient Temperature)
CL Load Capacitance
CIN Input Capacitance
−40 +85 °C
30 pF
7 pF
Table 6. ELECTRICAL CHARACTERISTICS
Parameter
Description
Test Conditions
VIL Input LOW Voltage (Note 10)
VIH Input HIGH Voltage (Note 10)
IIL Input LOW Current
VIN = 0 V
IIH Input HIGH Current
VIN = VDD
VOL
Output LOW Voltage (Note 11)
IOL = 8 mA
VOH
Output HIGH Voltage (Note 11)
IOH = −8 mA
IDD Supply Current
Unloaded outputs
Zo Output Impedance
10. CLKIN input has a threshold voltage of VDD/2
11. Parameter is guaranteed by design and characterization. Not 100% tested in production
Table 7. SWITCHING CHARACTERISTICS FOR ASM3P622S00B/E
Parameter
Test Conditions
Input Frequency
Output Frequency
30 pF load
Duty Cycle = (t2 / t1) * 100 (Notes 12, 13)
Output Rise Time (Notes 12, 13)
Measured at VDD/2
Measured between 0.8 V and 2.0 V
Output Fall Time (Notes 12, 13)
Measured between 2.0 V and 0.8 V
Output−to−output skew (Notes 12, 13)
All outputs equally loaded with SSOFF
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge (Note 13)
Measured at VDD/2 with SSOFF
Device−to−Device Skew (Note 13)
Measured at VDD/2 on the CLKOUT
pins of the device
Cycle−to−Cycle Jitter
(Notes 12, 13)
Loaded outputs
< 8 MHz
> 8 MHz
PLL Lock Time (Note 13)
Stable power supply, valid clock
presented on CLKIN pin
12. All parameters specified with 30 pF loaded outputs.
13. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Min
2.0
2.4
Min
4
4
40
Typ Max Unit
0.8 V
V
50 mA
100 mA
0.4 V
V
18 mA
23 W
Typ Max Unit
20 MHz
20 MHz
50 60 %
2.5 nS
2.5 nS
250 pS
±350
pS
700 pS
±1.6
±200
1.0
nS
pS
mS
http://onsemi.com
5
5 Page 
ASM3P622S00B, ASM3P622S00E
PACKAGE DIMENSIONS
TSSOP16, 4.4x5
CASE 948AN−01
ISSUE O
b
PIN#1
IDENTIFICATION
TOP VIEW
e
D
E1 E
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
L1
θ
MIN
0.05
0.85
0.19
0.13
4.90
6.30
4.30
0.45
0º
NOM
0.65 BSC
1.00 REF
MAX
1.10
0.15
0.95
0.30
0.20
5.10
6.50
4.50
0.75
8º
A2 A θ1
c
A1
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
END VIEW
L1
L
http://onsemi.com
11
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ASM3P622S00E.PDF ] | |
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