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PDF ASM2I99446 Data sheet ( Hoja de datos )
| Número de pieza | ASM2I99446 | |
| Descripción | 2.5V and 3.3V LVCMOS Clock Distribution Buffer | |
| Fabricantes | Alliance Semiconductor | |
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July 2005
ASM2I99446
rev 0.4
2.5V and 3.3V LVCMOS Clock Distribution Buffer
Features
Configurable 10 outputs LVCMOS clock
distribution buffer
Compatible to single, dual and mixed 3.3V/2.5V
Voltage supply
Wide range output clock frequency up to 250MHz
Designed for mid-range to high-performance
telecom, networking and computer applications
Supports applications requiring clock redundancy
Max. output skew of 200pS (150pS within one
bank)
Selectable output configurations per output bank
Tristatable outputs
32 lead LQFP & TQFP Packages
Ambient operating temperature range of
-
-40 to 85°C
Functional Description
The ASM2I99446 is a 2.5V and 3.3V compatible 1:10 clock
distribution buffer designed for low-voltage mid-range to
high-performance telecom, networking and computing
applications. Both 3.3V, 2.5V and dual supply voltages are
supported for mixed-voltage applications. The ASM2I99446
offers 10 low-skew outputs and 2 selectable inputs for clock
redundancy. The outputs are configurable and support 1:1
and 1:2 output to input frequency ratios. The ASM2I99446
is specified for the extended temperature range of -40°C to
85°C.
The ASM2I99446 is a full static fanout buffer design
supporting clock frequencies up to 250MHz. The signals
are generated and retimed on-chip to ensure minimal skew
between the three output banks. Two independent
LVCMOS compatible clock inputs are available. This
feature supports redundant clock sources or the addition of
a test clock into the system design. Each of the three
output banks can be individually supplied by 2.5V or 3.3V
supporting mixed voltage applications. The FSELx pins
choose between division of the input reference frequency
by one or two. The frequency divider can be set individually
for each of the three output banks. The ASM2I99446 can
be reset and the outputs are disabled by deasserting the
MR/OE pin (logic high state). Asserting MR/OE will enable
the outputs.
All inputs accept LVCMOS signals while the outputs
provide LVCMOS compatible levels with the capability to
drive terminated 50Ω transmission lines. Please consult the
ASM2I99456 specification for a 1:10 mixed voltage buffer
with LVPECL compatible inputs. For series terminated
transmission lines, each of the ASM2I99446 outputs can
drive one or two traces giving the devices an effective
fanout of 1:20. The device is packaged in a 7x7mm2
32-lead LQFP and TQFP Packages.
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
1 page  
July 2005
ASM2I99446
rev 0.4
Table 7: AC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 3.3V ±5%, TA = –40°C to +85°C)1
Symbol
fref
fMAX
tP, REF
tr, tf
tPLH
tPHL
tPLZ, HZ
tPZL, LZ
tsk(O)
tsk(PP)
tSK(P)
DCQ
Characteristics
Input Frequency
Maximum Output Frequency
÷1 output
÷2 output
Reference Input Pulse Width
CCLK Input Rise/Fall Time
Propagation delay
CCLK0,1 to any Q
CCLK0,1 to any Q
Output Disable Time
Output Enable Time
Output-to-output Skew
Within one bank
Any output Bank, Same output divider
Any output, Any output divider
Device-to-device Skew
Output pulse skew4
Output Duty Cycle
÷1 output
÷2 output
Min Typ
0
0
0
1.4
2.2 2.8
2.2 2.8
47 50
45 50
Max
2502
2502
125
1.03
4.45
4.2
10
10
150
200
350
2.25
200
53
55
Unit
MHz
MHz
MHz
nS
nS
nS
nS
nS
nS
pS
pS
pS
nS
pS
%
%
Condition
FSELx=0
FSELx=1
0.8 to 2.0V
DCREF = 50%
DCREF = 25%-75%
tr, tf Output Rise/Fall Time
0.1
1.0 nS
0.55 to 2.4V
Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT
2 The ASM2I99446 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz.
3 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
output duty cycle and maximum frequency specifications.
4 Output pulse skew is the absolute difference of the propagation delay times | tpLH - tpHL |.
Table 8: DC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V ±5%, TA = –40°C to +85°C)
Symbol
Characteristics
Min Typ
Max Unit
Condition
VIH Input High Voltage
1.7
VCC + 0.3
V LVCMOS
VIL Input Low Voltage
VOH Output High Voltage
-0.3 0.7 V LVCMOS
1.8 V IOH=-15 mA1
VOL Output Low Voltage
0.6 V IOL= 15 mA
ZOUT
Output Impedance
17 - 202
Ω
IIN Input Current2
±200
µA VIN=GND or VIN=VCC
ICCQ3
Maximum Quiescent Supply Current
2.0 mA All VCC Pins
Note: 1 The ASM2I99446 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to
a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines per output.
2 Input pull-up / pull-down resistors influence input current.
3 ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
2.5V and 3.3V LVCMOS Clock Distribution Buffer
Notice: The information in this document is subject to change without notice.
5 of 14
5 Page 
July 2005
rev 0.4
Package Information
32-lead TQFP Package
ASM2I99446
SECTION A-A
Symbol
A
A1
A2
D
D1
E
E1
L
L1
T
T1
b
b1
R0
a
e
Dimensions
Inches
Millimeters
Min Max Min Max
….
0.0472
…
1.2
0.0020
0.0059
0.05
0.15
0.0374
0.0413
0.95
1.05
0.3465
0.3622
8.8
9.2
0.2717
0.2795
6.9
7.1
0.3465
0.3622
8.8
9.2
0.2717
0.2795
6.9
7.1
0.0177
0.0295
0.45
0.75
0.03937 REF
1.00 REF
0.0035
0.0079
0.09
0.2
0.0038
0.0062
0.097
0.157
0.0118
0.0177
0.30
0.45
0.0118
0.0157
0.30
0.40
0.0031
0.0079
0.08
0.2
0° 7° 0° 7°
0.031 BASE
0.8 BASE
2.5V and 3.3V LVCMOS Clock Distribution Buffer
14
Notice: The information in this document is subject to change without notice.
11 of
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| PDF Descargar | [ Datasheet ASM2I99446.PDF ] | |
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