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Número de pieza ASM2I9942C
Descripción Low Voltage 1:18 Clock Distribution Chip
Fabricantes Alliance Semiconductor 
Logotipo Alliance Semiconductor Logotipo



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May 2005
ASM2I9942C
rev 0.2
Low Voltage 1:18 Clock Distribution Chip
Features
ƒ LVCMOS/LVTTL Clock Input
ƒ 2.5V LVCMOS Outputs for Pentium IITM*
Microprocessor Support
ƒ 150pS Maximum Targeted Output–to–Output Skew
ƒ Maximum Output Frequency of 250MHz @ 3.3 VCC
ƒ 32–Lead TQFP and LQFP Packaging
ƒ Single 3.3V or 2.5V Supply.
ƒ Pin and Function compatible to MPC942C.
Functional Description
The ASM2I9942C is a 1:18 low voltage clock distribution
chip with 2.5V or 3.3V LVCMOS output capabilities. The
device is offered in two versions; the ASM2I9942C has an
LVCMOS input clock while the ASM2I9942P has an
LVPECL input clock. The 18 outputs are 2.5V or 3.3V
LVCMOS compatible and feature the drive strength to drive
50series or parallel terminated transmission lines. With
output–to–output skews of 200pS, the ASM2I9942C is
ideal as a clock distribution chip for the most demanding of
synchronous systems. The 2.5V outputs also make the
device ideal for supplying clocks for a high performance
Pentium II TM microprocessor based design.
With a low output impedance (12), in both the HIGH and
LOW logic states, the output buffers of the ASM2I9942C
are ideal for driving series terminated transmission lines.
With an output impedance of 12, the ASM2I9942C can
drive two series terminated transmission lines from each
output. This capability gives the ASM2I9942C an effective
fanout of 1:36. The ASM2I9942C provides enough copies
of low skew clocks for most high performance synchronous
systems.
The LVCMOS/LVTTL input of the ASM2I9942C provides a
more standard LVCMOS interface. The OE pins will place
the outputs into a high impedance state. The OE pin has an
internal pullup resistor.
The ASM2I9942C is a single supply device. The VCC power
pins require either 2.5V or 3.3V. The 32–lead TQFP and
LQFP package is chosen to optimize performance, board
space and cost of the device. The 32–lead TQFP has a
7x7mm2 body size with a conservative 0.8mm pin spacing.
*Pentium II is a trademark of Intel Corporation
Alliance Semiconductor
2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.

1 page




ASM2I9942C pdf
May 2005
rev 0.2
Power Consumption of the ASM2I9942C and
Thermal Management
The ASM2I9942C AC specification is guaranteed for the
entire operating frequency range up to 250MHz. The
ASM2I9942C power consumption and the associated
long-term reliability may decrease the maximum
frequency limit, depending on operating conditions such
as clock frequency, supply voltage, output loading,
ambient temperature, vertical convection and thermal
conductivity of package and board. This section
describes the impact of these parameters on the junction
temperature and gives a guideline to estimate the
ASM2I9942C die junction temperature and the
associated device reliability.
Table 8. Die junction temperature and MTBF
Junction temperature (°C)
100
110
120
130
MTBF (Years)
20.4
9.1
4.2
2.0
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable
MTBF, the die junction temperature of the ASM2I9942C
needs to be controlled and the thermal impedance of the
board/package should be optimized. The power
dissipated in the ASM2I9942C is represented in
equation1.
ASM2I9942C
Where ICCQ is the static current consumption of the
ASM2I9942C, CPD is the power dissipation capacitance
per output, (Μ)ΣCL represents the external capacitive
output load, N is the number of active outputs (N is
always 12 in case of the ASM2I9942C). The
ASM2I9942C supports driving transmission lines to
maintain high signal integrity and tight timing parameters.
Any transmission line will hide the lumped capacitive load
at the end of the board trace, therefore, ΣCL is zero for
controlled transmission line systems and can be
eliminated from equation 1. Using parallel termination
output termination results in equation 2 for power
dissipation.
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination. VOL, IOL, VOH and IOH are
a function of the output termination technique and DCQ is
the clock signal duty cycle. If transmission lines are used
ΣCL is zero in equation 2 and can be eliminated. In
general, the use of controlled transmission line
techniques eliminates the impact of the lumped capacitive
loads at the end lines and greatly reduces the power
dissipation of the device. Equation 3 describes the die
junction temperature TJ as a function of the power
consumption.
Where Rthja is the thermal impedance of the package
(junction to ambient) and TA is the ambient temperature.
According to Table 8, the junction temperature can be
used to estimate the long-term device reliability. Further,
combining equation 1 and equation 2 results in a
maximum operating frequency for the ASM2I9942C in a
series terminated transmission line system, equation 4.
PTOT
=
I
CCQ
+ VCC
f CLOCK
⋅  N CPD
+
CL  ⋅VCC
  M 
Equation1
∑ ∑[ ( ) ]PTOT
= VCC
I
CCQ
+ VCC
f CLOCK
⋅  N CPD
+
CL  +
( )DCQ IOH VCC VOH + 1DCQ IOL VOL
  M  P
TJ = TA + PTOT Rthja
Equation 2
Equation 3
( )fCLOCKMAX
=
1
CPD N VC2C
TJ

,MAX
Rthja
TA
I CCQ VCC

Equation 4
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
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