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PDF ASM2P5T905A Data sheet ( Hoja de datos )
| Número de pieza | ASM2P5T905A | |
| Descripción | 2.5V Single Data Rate 1:5 Clock Buffer Terabuffer | |
| Fabricantes | PulseCore | |
| Logotipo |  |
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November 2006
rev 0.2
ASM2P5T905A
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Features
• Guaranteed Low Skew < 25pS (max)
• Very low duty cycle distortion
• High speed propagation delay < 2.5nS. (max)
• Up to 250MHz operation
• Very low CMOS power levels
• 1.5V VDDQ for HSTL interface
• Hot insertable and Over-voltage tolerant inputs
• 3 level inputs for selectable interface
• Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or
LVEPECL input interface
• Selectable differential or single-ended inputs and
five single ended outputs
• 2.5V Supply Voltage
• Available in TSSOP Package
Functional Description
The ASM2P5T905A 2.5V single data rate (SDR) Clock
buffer is a user-selectable single-ended or differential input
Block Diagram
TxS
to five single-ended outputs buffer built on advanced metal
CMOS technology. The SDR Clock buffer fanout from a
single or differential input to five single-ended outputs
reduces the loading on the preceding driver and provides
an efficient clock distribution network. The ASM2P5T905A
can act as a translator from a differential HSTL, eHSTL,
1.8V/2.5V LVTTL, LVEPECL or single-ended 1.8V/2.5V
LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs.
Selectable interface is controlled by 3 level input signals
that may be hard-wired to appropriate high-mid-low levels.
Multiple power and grounds reduce noise.
Applications:
ASM2P5T905A is targeted towards Clock and signal
distribution.
GL
G
OUTPUT
Q1
CONTROL
RxS
A
A/VREF
OUTPUT
CONTROL
OUTPUT
CONTROL
Q2
Q3
OUTPUT
CONTROL
Q4
OUTPUT
CONTROL
Q5
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
1 page  
November 2006
rev 0.2
ASM2P5T905A
DC Electrical Characteristics over Operating Range
Symbol
VIHH
VIMM
VILL
Parameter
Input HIGH Voltage Level1
Input MID Voltage Level1
Input LOW Voltage Level1
I3
3-Level Input DC Current
(RxS, TxS)
Test Conditions
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
VIN= VDD
VIN= VDD/2
HIGH Level
MID Level
VIN= GND
LOW Level
Min
VDD- 0.4
VDD/2- 0.2
-50
-200
Max
VDD/2 + 0.2
0.4
200
+50
NOTE:
1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2.
DC Electrical Characteristics over Operating Range for HSTL1
Unit
V
V
V
µA
Symbol
Parameter
Input Characteristics
IIH Input HIGH Current9
IIL Input LOW Current9
VIK Clamp Diode Voltage
VIN DC Input Voltage
VDIF DC Differential Voltage2,8
VCM
DC Common Mode Input
Voltage3,8
VIH DC Input HIGH4,5,8
VIL DC Input LOW4,6,8
VREF
Single-Ended Reference
Voltage4,8
Output Characteristics
VOH Output HIGH Voltage
VOL Output LOW Voltage
Test Conditions
Min
VDD= 2.6V VI = VDDQ/GND
VDD= 2.6V VI = GND/VDDQ
VDD= 2.4V, IIN = -18mA
-0.3
0.2
680
VREF+ 100
Typ7
-0.7
750
750
Max Unit
±5
±5
- 1.2
+3.6
900
VREF-100
µA
V
V
V
mV
mV
mV
mV
IOH= -8mA
IOH= -100µA
IOL= 8mA
IOL= 100µA
VDDQ- 0.4
VDDQ- 0.1
V
V
0.4 V
0.1 V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input
level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential
voltage must be achieved to guarantee switching to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF.
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface
table should be referenced.
9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
5 of 19
5 Page 
November 2006
rev 0.2
DC Electrical Characteristics over Operating Range for 1.8V LVTTL1
ASM2P5T905A
Symbol
Parameter
Input Characteristics
IIH Input HIGH Current12
IIL Input LOW Current12
VIK Clamp Diode Voltage
VIN DC Input Voltage
Single-Ended Inputs2
VIH DC Input HIGH
VIL DC Input LOW
Differential Inputs
VDIF DC Differential Voltage3,9
VCM
DC Common Mode Input
Voltage4,9
VIH DC Input HIGH5,6,9
VIL DC Input LOW5,7,9
VREF
Single-Ended Reference
Voltage5,9
Output Characteristics
VOH Output HIGH Voltage
VOL Output LOW Voltage
Test Conditions
Min.
Typ8
Max
Unit
VDD = 2.6V VI = VDDQ/GND
VDD = 2.6V VI = GND/VDDQ
VDD = 2.4V, IIN= -18mA
- 0.3
1.07310
±5
±5
-0.7 - 1.2
VDDQ+ 0.3
0.68311
µA
V
V
V
V
0.2 V
825 900 975 mV
VREF+ 100
VREF- 100
mV
mV
900 mV
IOH= -6mA
IOH= -100µA
IOL= 6mA
IOL= 100µA
VDDQ- 0.4
VDDQ- 0.1
V
V
0.4 V
0.1 V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 1.8V LVTTL single-ended operation, the RxS pin is allowed to float or tied to VDD/2 and A/VREF is tied to GND.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input
level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential
voltage must be achieved to guarantee switching to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation in differential mode, A/VREF is tied to the DC voltage VREF. The input is guaranteed to toggle within ±200mV of VREF when VREF is
constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the A input. To guarantee switching in voltage
range specified in the JEDEC 1.8V LVTTL interface specification, VREF must be maintained at 900mV with appropriate tolerances.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface
table should be referenced.
10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 • VDD where VDD
is 1.8V ±0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator
was designed to accept the calculated worst case value (VIH = 0.65 • [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply.
11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 • VDD where VDD
is 1.8V ± 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator
was designed to accept the calculated worst case value (VIH = 0.35 • [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply.
12. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
2.5V Single Data Rate 1:5 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ASM2P5T905A.PDF ] | |
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