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PDF ASM2I2310ANZ Data sheet ( Hoja de datos )
| Número de pieza | ASM2I2310ANZ | |
| Descripción | 3.3V SDRAM Buffer | |
| Fabricantes | Alliance Semiconductor | |
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June 2005
rev 0.4
ASM2I2310ANZ
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Features
One input to 10 output buffer/driver
Supports up to four SDRAM SO-DIMMs
Two additional outputs for feedback
Serial interface for output control
Low skew outputs
Up to 133MHz operation
Multiple VDD and VSS pins for noise reduction
Dedicated OE pin for testing
Space-saving 28 Pin SSOP package
3.3V operation
Functional Description
The ASM2I2310ANZ is a 3.3V buffer designed to distribute
high-speed clocks in mobile PC applications. The part has
10 outputs, 8 of which can be used to drive up to four
SDRAM SO-DIMMs, and the remaining can be used for
external feedback to a PLL. The device operates at 3.3V
and outputs can run up to 133MHz, thus making it
compatible with Pentium II®i processors.
The ASM2I2310ANZ also includes a serial interface (IIC),
which can enable or disable each output clock. The IIC is
Slave Receiver only and is Standard mode compliant. IIC
Master can write into the IIC registers but cannot read
back. The first two bytes after address should be ignored
by IIC Block and data is valid after these two bytes as given
in IIC Byte Flow Table. On power-up, all output clocks are
enabled. A separate Output Enable pin facilitates testing on
ATE.
Block Diagram
BUF_IN
SDATA
SCLOCK
OE
i Pentium II is a registered trademark of Intel Corporation
Serial Interface
Decoding
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
1 page  
June 2005
rev 0.4
Switching Characteristics1
Parameter
fmax
tD
t3
Name
Maximum Operating Frequency
Duty Cycle2,3 = t2 ÷ t1
Rising Edge Rate3
t4
t5
t6
t7
tPLZ, tPHZ
tPZL, tPZH
tr
tf
Falling Edge Rate3
Output to Output Skew3
SDRAM Buffer LH Prop. Delay3
SDRAM Buffer HL Prop. Delay3
SDRAM Buffer Enable Delay3
SDRAM Buffer Disable Delay3
Rise Time for SDATA
(Refer Test Circuit for IIC)
Refer figure no.3
Fall Time for SDATA
(Refer Test Circuit for IIC)
Refer figure no.3
Test Conditions
Measured at 1.5V
Measured between 0.4V and
2.4V
Measured between 2.4V and
0.4V
All outputs equally loaded
Input edge greater than 1 V/nS
Input edge greater than 1 V/nS
Input edge greater than 1 V/nS
Input edge greater than 1 V/nS
CL = 10pF
CL = 400pF
CL = 10pF
CL = 400pF
Note: 1 .All parameters specified with loaded outputs.
2. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/nS
3. Parameter is guaranteed by design and characterization. Not 100% tested in production.
ASM2I2310ANZ
Min Typ Max Unit
133 MHz
45.0 50.0 55.0
%
1 2 4 V/nS
1 2 4 V/nS
150 225 pS
1 2.7 3.5 nS
1 2.7 3.5 nS
1 3 5 nS
1 3 5 nS
6
250 nS
20
250 nS
Test Circuit for SDRAM Enable and Disable Times
PULSE
GENERATOR
VI
VDD
D.U.T
RT
VO
CL
S1 2 * VDD
Open
VSS
500Ω
500Ω
TEST
t6/t7
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2* VDD
VSS
Figure 1. Load circuit for Switching times
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
5 of 12
5 Page 
June 2005
rev 0.4
Ordering Information
Part Number
ASM2I2310ANZ-28-AT
ASM2I2310ANZ-28-AR
ASM2I2310AGNZ-28-AT
ASM2I2310AGNZ-28-AR
Marking
2I2310ANZ
2I2310ANZ
2I2310AGNZ
2I2310AGNZ
Package Type
28-pin SSOP –Tube
28-pin SSOP –Tape and Reel
28-pin SSOP –Tube, Green
28-pin SSOP –Tape and Reel, Green
Device Ordering Information
ASM2I2310ANZG-28-AR
ASM2I2310ANZ
Operating Range
Industrial
Industrial
Industrial
Industrial
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
DEVICE PIN COUNT
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive I= Industrial P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs
Notice: The information in this document is subject to change without notice.
11 of 12
11 Page | ||
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| PDF Descargar | [ Datasheet ASM2I2310ANZ.PDF ] | |
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