PDF ASM2P20805A Data sheet ( Hoja de datos )

Número de pieza	ASM2P20805A
Descripción	2.5V CMOS Dual 1-To-5 Clock Driver
Fabricantes	Alliance Semiconductor
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No Preview Available ! June 2005 ASM2P20805A rev 0.2 2.5V CMOS Dual 1-To-5 Clock Driver Features Advanced CMOS Technology Guaranteed low skew < 200pS (max.) Very low propagation delay < 2.5nS (max) Very low duty cycle distortion < 270pS (max) Very low CMOS power levels Operating frequency up to 166MHz TTL compatible inputs and outputs Two independent output banks with 3-state control 1:5 fanout per bank "Heartbeat" monitor output VCC = 2.5V ± 0.2V Available in SSOP and QSOP packages Functional Description The ASM2P20805A is a 2.5V Clock driver built using advanced CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The ASM2P20805A offers low capacitance inputs. The ASM2P20805A is designed for high speed clock distribution where signal quality and skew are critical. The ASM2P20805A also allows single point-to- point transmission line driving in applications such as address distribution, where one signal must be distributed to multiple receivers with low skew and high signal quality. Block Diagram OEA INA INB OEB 5 OA1 – OA5 5 OB1 – OB5 MON Pin Diagram VCCA OA1 OA2 OA3 GNDA OA4 OA5 GNDQ OEA INA 1 20 2 A 19 3 S 18 4 M 2 17 5 P 16 2 6 0 15 7 8 14 0 8 5 13 9 A 12 10 11 VCCB OB1 OB2 OB3 GNDB OB4 OB5 MON OEB INB Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. 1 page June 2005 ASM2P20805A rev 0.2 Switching Characteristics Over Operating Range3,4 Symbol Parameter Conditions1 Min2 Max Unit tPLH Propagation Delay tPHL INA to OAn, INB to OBn tR Output Rise Time (Measured from 0.8V to 2V) tF Output Fall Time (Measured from 2V to 0.8V) 1 3 nS - 1.5 nS - 1.5 nS tSK(O) Same device output pin to pin skew5 - 270 pS tSK(P) Pulse skew6,9 CL= 15pF f ≤133MHz - 270 pS tSK(PP) tPZL tPZH tPLZ tPHZ fMAX tPLH tPHL tR tF tSK(O) Part to part skew7 Output Enable Time O¯¯EA to OAn, O¯¯EB to OBn Output Disable Time O¯¯EA to OAn, O¯¯EB to OBn Input Frequency Propagation Delay INA to OAn, INB to OBn Output Rise Time (Measured from 0.7V to 1.7V) Output Fall Time (Measured from 1.7V to 0.7V) Same device output pin to pin skew5 tSK(P) Pulse skew6,9 CL= 15pF 133MHz ≤ f ≤166MHz - - - - 0.5 - - - - 550 pS 5.2 nS 5.2 nS 133 MHz 2.5 nS 1.25 nS 1.25 nS 200 pS 270 pS tSK(PP) Part to part skew7 - 550 pS tPZL Output Enable Time tPZH O¯¯EA to OAn, O¯¯EB to OBn tPLZ Output Disable Time tPHZ O¯¯EA to OAn, O¯¯EB to OBn - 5.2 nS - 5.2 nS fMAX Input Frequency - 166 MHz Notes: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH and tPHL are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 5. Skew measured between all outputs under identical transitions and load conditions. 6. Skew measured is difference between propagation delay times tPHL and tPLH of same outputs under identical load conditions. 7. Part to part skew for all outputs given identical transitions and load conditions at identical VCC levels and temperature. 8. Airflow of 1m/s is recommended for frequencies above 133MHz. 9. This parameter is measured using f = 1MHz. 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 5 of 11 5 Page June 2005 rev 0.2 ASM2P20805A Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM2P20805A Document Version: 0.2 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale which are available from Alliance. All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 2.5V CMOS Dual 1-To-5 Clock Driver Notice: The information in this document is subject to change without notice. 11 of 11 11 Page

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